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| IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. Company name - NXP B.V. is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) NXP B.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.nxp.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless www.stnwireless.com ISP1583 Hi-Speed USB peripheral controller Rev. 07 -- 22 September 2008 Product data sheet 1. General description The ISP1583 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus (USB) peripheral controller. It fully complies with Ref. 1 "Universal Serial Bus Specification Rev. 2.0", supporting data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s). The ISP1583 provides high-speed USB communication capacity to systems based on microcontrollers or microprocessors. It communicates with a microcontroller or microprocessor of a system through a high-speed general-purpose parallel interface. The ISP1583 supports automatic detection of Hi-Speed USB system operation. Original USB fall-back mode allows the device to remain operational under full-speed conditions. It is designed as a generic USB peripheral controller so that it can fit into all existing device classes, such as imaging class, mass storage devices, communication devices, printing devices and human interface devices. The ISP1583 is a low-voltage device, which supports I/O pad voltages from 1.65 V to 3.6 V. The internal generic Direct Memory Access (DMA) block allows easy integration into data streaming applications. In addition, the various configurations of the DMA block are tailored for mass storage applications. The modular approach to implementing a USB peripheral controller allows the designer to select the optimum system microcontroller from the wide variety available. The ability to reuse existing architecture and firmware shortens the development time, eliminates risk and reduces cost. The result is fast and efficient development of the most cost-effective USB peripheral solution. The ISP1583 also incorporates features such as SoftConnect, a reduced frequency crystal oscillator and integrated termination resistors. These features allow significant cost savings in system design and easy implementation of advanced USB functionality into PC peripherals. 2. Features I Complies fully with: N Ref. 1 "Universal Serial Bus Specification Rev. 2.0" N Most device class specifications N ACPI, OnNow and USB power management requirements I Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s) I Direct interface to ATA/ATAPI peripherals; applicable only in split bus mode I High performance USB peripheral controller with integrated Serial Interface Engine (SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller I I I I I I I I I I I I I I I I I I I I Automatic Hi-Speed USB mode detection and Original USB fall-back mode Supports sharing mode Supports I/O voltage range of 1.65 V to 3.6 V Supports VBUS sensing High-speed DMA interface Configurable direct access data path from the microprocessor to an ATA device Fully autonomous and multiconfiguration DMA operation Seven IN endpoints, seven OUT endpoints, and a fixed control IN and OUT endpoint Integrated physical 8 kB of multiconfiguration FIFO memory Endpoints with double buffering to increase throughput and ease real-time data transfer Bus-independent interface with most microcontrollers and microprocessors 12 MHz crystal oscillator with integrated PLL for low EMI Software-controlled connection to the USB bus (SoftConnect) Low-power consumption in operation and power-down modes; suitable for use in bus-powered USB devices Supports Session Request Protocol (SRP) that adheres to Ref. 2 "On-The-Go Supplement to the USB Specification Rev. 1.3" Internal power-on and low-voltage reset circuits; also supports software reset Operation over the extended USB bus voltage range (DP, DM and VBUS) 5 V tolerant I/O pads Operating temperature range from -40 C to +85 C Available in HVQFN64 and TFBGA64 halogen-free and lead-free packages 3. Applications I I I I I I I I I Personal digital assistant Mass storage device, for example: CD, DVD, Magneto-Optical (MO) and Zip drives Digital video camera Digital still camera 3G mobile phone MP3 player Communication device, for example: router and modem Printer Scanner ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 2 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 4. Ordering information Table 1. Ordering information Package Name ISP1583BS ISP1583ET ISP1583ET1[1] ISP1583ET2[1] [1] Type number Description Version HVQFN64 TFBGA64 TFBGA64 TFBGA64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; SOT804-1 body 9 x 9 x 0.85 mm plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm plastic thin fine-pitch ball grid array package; 64 balls; body 4 x 4 x 0.8 mm plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm SOT543-1 SOT969-1 SOT543-1 Contains solder ball material SAC105. 5. Marking Table 2. Marking codes Marking code[1] ISP1583BS ISP1583 1583 1583ET2 Type number ISP1583BS ISP1583ET ISP1583ET1 ISP1583ET2 [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 3 of 99 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data sheet Rev. 07 -- 22 September 2008 (c) NXP B.V. 2008. All rights reserved. ISP1583_7 6. Block diagram NXP Semiconductors to or from USB DP DM 12 MHz VBUS XTAL1 XTAL2 CS1_N DA1(2) DREQ CS0_N DA0(3) DA2 DIOR DACK DIOW 10 11 12 8 EOT INTRQ IORDY(1) 3 3.3 V 1.5 k 4 55 58 57 21 22 62 60 17 9 ISP1583 SoftConnect DMA HANDLER DMA INTERFACE 14 15 RPU 2 37 to 40, 42 to 53 DMA REGISTERS 62 60 34 MICROCONTROLLER HANDLER MICROCONTROLLER INTERFACE SYSTEM CONTROLLER I/O pad supply 13, 35, 59 1, 5 32, 56 64 63 26, 41, 54 VCC(I/O) 004aaa268 16 RREF 12 k 6 HI-SPEED USB TRANSCEIVER NXP SIE/PIE MEMORY MANAGEMENT UNIT DATA[15:0] BUS_CONF(3) MODE0(2) MODE1 8 RESET_N 7 POWER-ON RESET internal reset analog supply 23 to 25, 27 to 31 18 36 19 20 INTEGRATED RAM (8 kB) AD[7:0] CS_N ALE/A0 RW_N/RD_N DS_N/WR_N READY(1) INT VCC(3V3) 61 VOLTAGE 1.8 V digital REGULATORS supply OTG SRP MODULE 15 16 Hi-Speed USB peripheral controller DGND AGND VCC1V8 SUSPEND WAKEUP The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see Table 3. The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register). (1) Pin 15 is shared by READY and IORDY. (2) Pin 60 is shared by MODE0 and DA1. (3) Pin 62 is shared by BUS_CONF and DA0. ISP1583 4 of 99 Fig 1. Block diagram NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 7. Pinning information 7.1 Pinning BUS_CONF/DA0 MODE0/DA1 SUSPEND WAKEUP VCC(3V3) VCC1V8 DATA15 DATA13 XTAL1 XTAL2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 terminal 1 index area AGND RPU DP DM AGND RREF RESET_N EOT DREQ DACK DIOR DIOW DGND INTRQ READY/IORDY INT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DATA14 DGND DATA12 VBUS DATA11 VCC(I/O) 48 47 46 45 44 43 42 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 VCC(I/O) DATA3 DATA2 DATA1 DATA0 ALE/A0 DGND MODE1 n.c. ISP1583BS 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AD7 AD1 CS1_N AD0 AD2 AD4 AD5 AD6 RW_N/RD_N DS_N/WR_N VCC1V8 CS0_N DA2 VCC(I/O) CS_N AD3 32 004aaa537 (c) NXP B.V. 2008. All rights reserved. Transparent top view Fig 2. Pin configuration ISP1583BS (top view) ball A1 index area 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K ISP1583ET; ISP1583ET2 004aaa859 Transparent top view Fig 3. ISP1583_7 Pin configuration ISP1583ET and ISP1583ET2 (top view) Product data sheet Rev. 07 -- 22 September 2008 5 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller ISP1583ET1 ball A1 index area A B C D E F G H 004aaa991 12345678 Transparent top view Fig 4. Pin configuration ISP1583ET1 (top view) 7.2 Pin description Table 3. Symbol[1] Pin description Pin ISP1583BS ISP1583ET; ISP1583ET1 ISP1583ET2 AGND RPU DP DM AGND RREF RESET_N 1 2 3 4 5 6 7 D2 A1 B1 C1 D1 E2 D2 A1 B1 C1 D1 C3 A A A A I analog ground pull-up resistor connection; this pin must be connected to 3.3 V through an external 1.5 k resistor to pull up pin DP USB D+ line connection (analog) USB D- line connection (analog) analog ground external bias resistor connection; this pin must be connected to ground through a 12.0 k 1 % resistor reset input (500 s); a LOW level produces an asynchronous reset; connect to VCC(3V3) for power-on reset (internal POR circuit) When the RESET_N pin is LOW, ensure that the WAKEUP pin does not go from LOW to HIGH; otherwise the device will enter test mode. TTL; 5 V tolerant EOT 8 E1 D3 I end-of-transfer input (programmable polarity); used in DMA slave mode only; when not in use, connect this pin to VCC(I/O) through a 10 k resistor input pad; TTL; 5 V tolerant DREQ 9 F2 E1 I/O DMA request input or output (programmable polarity); the signal direction depends on bit MASTER in register DMA Hardware (see Table 59): Type[2] Description * * Input: DMA master mode if bit MASTER = 1 Output: DMA slave mode if bit MASTER = 0 When not in use, in the default setting, this pin must be connected to ground through a 10 k resistor. bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 6 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 3. Symbol[1] Pin description ...continued Pin ISP1583BS ISP1583ET; ISP1583ET1 ISP1583ET2 Type[2] Description DACK 10 F1 E2 I/O DMA acknowledge input or output (programmable polarity); the signal direction depends on bit MASTER in register DMA Hardware (see Table 59): * * Input: DMA slave mode if bit MASTER = 0 Output: DMA master mode if bit MASTER = 1 When not in use, in the default setting, this pin must be connected to VCC(I/O) through a 10 k resistor. bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DIOR 11 G2 E3 I/O DMA read strobe input or output (programmable polarity); the signal direction depends on bit MASTER in register DMA Hardware (see Table 59): * * Input: DMA slave mode if bit MASTER = 0 Output: DMA master mode if bit MASTER = 1 When not in use, in the default setting, this pin must be connected to VCC(I/O) through a 10 k resistor. bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DIOW 12 G1 F1 I/O DMA write strobe input or output (programmable polarity); the signal direction depends on bit MASTER in register DMA Hardware (see Table 59): * * Input: DMA slave mode if bit MASTER = 0 Output: DMA master mode if bit MASTER = 1 When not in use, in the default setting, this pin must be connected to VCC(I/O) through a 10 k resistor. bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant DGND INTRQ 13 14 H2 H1 F2 G2 I digital ground interrupt request input; from the ATA/ATAPI peripheral; use a 10 k resistor to pull down input pad; TTL; 5 V tolerant READY/ IORDY 15 J1 G1 I/O Signal ready output -- Used in generic processor mode: * * LOW: the ISP1583 is processing a previous command or data and is not ready for the next command or data transfer HIGH: the ISP1583 is ready for the next microprocessor read or write I/O ready input -- Used in split bus mode to access ATA/ATAPI peripherals (PIO mode only) bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant INT 16 K1 H1 O interrupt output; programmable polarity (active HIGH or LOW) and signaling (edge or level triggered) CMOS output; 8 mA drive DA2[3] 17 J2 H2 O address output to select the Task File register of an ATA/ATAPI device; see Table 61 CMOS output; 8 mA drive CS_N 18 K2 E4 I chip selection input input pad; TTL; 5 V tolerant ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 7 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 3. Symbol[1] Pin description ...continued Pin ISP1583BS ISP1583ET; ISP1583ET1 ISP1583ET2 Type[2] Description RW_N/ RD_N 19 J3 F3 I Read or write input -- For the Freescale mode, this function is determined by pin MODE0 = LOW during power-up. Read input -- For the 8051 mode, this function is determined by pin MODE0 = HIGH during power-up. input pad; TTL; 5 V tolerant DS_N/ WR_N 20 K3 H3 I Data selection input -- For the Freescale mode, this function is determined by pin MODE0 = LOW at power-up. Write input -- For the 8051 mode, this function is determined by pin MODE0 = HIGH at power-up. input pad; TTL; 5 V tolerant CS0_N[3] 21 J4 G3 O chip selection output 0 for the ATA/ATAPI device; see Table 61 CMOS output; 8 mA drive chip selection output 1 for the ATA/ATAPI device; see Table 61 CMOS output; 8 mA drive bit 0 of the multiplexed address and data bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 1 of the multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 2 of the multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16 bit 3 of the multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 4 of the multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 5 of the multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 6 of the multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 7 of the multiplexed address and data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant voltage regulator output (1.8 V 0.15 V); tapped out voltage from the internal regulator; this regulated voltage cannot drive external devices; decouple this pin using a 0.1 F capacitor; see Section 8.16 not connected CS1_N[3] 22 K4 F4 O AD0 AD1 AD2 VCC(I/O)[4] AD3 AD4 AD5 AD6 AD7 23 24 25 26 27 28 29 30 31 K5 J5 K6 J6 K7 J7 K8 J8 K9 K10 G4 H4 F5 E5 H5 G5 G6 H6 H7 H8 I/O I/O I/O I/O I/O I/O I/O I/O - VCC1V8[4] 32 n.c. 33 - - - ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 8 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 3. Symbol[1] Pin description ...continued Pin ISP1583BS ISP1583ET; ISP1583ET1 ISP1583ET2 Type[2] Description MODE1 34 J10 G8 I mode selection input 1; used in split bus mode only: * * LOW: ALE function (address latch enable) HIGH (connect to VCC(I/O)): A0 function (address/data indicator) Remark: When operating in generic processor mode, set pin MODE1 as HIGH. input pad; TTL; 5 V tolerant DGND ALE/A0 35 36 H9 H10 F8 F7 I digital ground Address latch enable input -- When pin MODE1 = LOW during power-up, a falling edge on this pin latches the address on the multiplexed address and data bus AD[7:0]. Address and data selection input -- When pin MODE1 = HIGH during power-up, the function is determined by the level on this pin (detected on the rising edge of the WR_N pulse): * * HIGH: bus AD[7:0] is a register address LOW: bus AD[7:0] is register data; used in split bus mode only Remark: When operating in generic processor mode with pin MODE1 = HIGH, this pin must be pulled down using a 10 k resistor. input pad; TTL; 5 V tolerant DATA0 DATA1 DATA2 DATA3 VCC(I/O)[4] DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 37 38 39 40 41 42 43 44 45 46 47 G9 G10 F9 F10 E9 E10 D10 D9 C10 C9 B10 F6 E6 E7 E8 D7 D6 D8 D5 D4 C8 C7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O bit 0 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 1 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 2 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 3 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16 bit 4 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 5 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 6 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 7 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 8 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 9 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 9 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 3. Symbol[1] Pin description ...continued Pin ISP1583BS ISP1583ET; ISP1583ET1 ISP1583ET2 Type[2] Description DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VCC(I/O)[4] VBUS 48 49 50 51 52 53 54 55 A10 A9 B8 A8 B7 A7 B6 B5 A8 C4 B7 A7 C6 C5 B6 A6 I/O I/O I/O I/O I/O I/O A bit 10 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 11 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 12 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 13 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 14 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant bit 15 of the bidirectional data bus bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16 USB bus power sensing input -- Used to detect whether the host is connected or not; connect a 1 F electrolytic or tantalum capacitor and a 1 M pull-down resistor to ground; see Section 8.14 VBUS pulsing output -- In OTG mode; connect a 1 F electrolytic or tantalum capacitor and a 1 M pull-down resistor to ground; see Section 8.14 5 V tolerant VCC1V8[4] 56 A6 B5 - voltage regulator output (1.8 V 0.15 V); tapped out voltage from the internal regulator; this regulated voltage cannot drive external devices; decouple this pin using 4.7 F and 0.1 F capacitors; see Section 8.16 crystal oscillator output (12 MHz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin XTAL1; see Table 100 crystal oscillator input (12 MHz); connect a fundamental parallel-resonant crystal or an external clock source (leaving pin XTAL2 unconnected); see Table 100 digital ground Mode selection input 0 -- Selects the read/write strobe functionality in generic processor mode during power-up: XTAL2 57 A5 A5 O XTAL1 58 A4 A4 I DGND MODE0/ DA1[3] 59 60 B4 A3 B4 C2 I/O * * LOW: for the Freescale mode; the function of pin 19 is RW_N and pin 20 is DS_N HIGH (connect to VCC(I/O)): for the 8051 mode; the function of pin 19 is RD_N and pin 20 is WR_N Address selection output -- Selects the Task File register of an ATA/ATAPI device during normal operation; see Table 61 bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant VCC(3V3)[4] 61 B3 B3 regulator supply voltage (3.3 V 0.3 V); this pin supplies the internal regulator; see Section 8.16 ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 10 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 3. Symbol[1] Pin description ...continued Pin ISP1583BS ISP1583ET; ISP1583ET1 ISP1583ET2 Type[2] Description BUS_ CONF/ DA0[3] 62 B2 A3 I/O Bus configuration input -- Selects bus mode during power-up: * * LOW: split bus mode; multiplexed 8-bit address and data bus on AD[7:0], separate DMA data bus DATA[15:0][5] HIGH (connect to VCC(I/O)): generic processor mode; separate 8-bit address on AD[7:0], 16-bit processor data bus on DATA[15:0]; DMA is multiplexed on processor bus DATA[15:0] Address selection output -- Selects the Task File register of an ATA/ATAPI device at normal operation; see Table 61 bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant WAKEUP 63 A2 B2 I wake-up input; when this pin is at the HIGH level, the chip is prevented from going into the suspend state and wake-up the chip when already in suspend mode; when not in use, connect this pin to ground through a 10 k resistor When the RESET_N pin is LOW, ensure that the WAKEUP pin does not go from LOW to HIGH; otherwise the device will enter test mode. input pad; TTL; 5 V tolerant SUSPEND 64 C2 A2 O suspend state indicator output; used as a power switch control output to power-off or power-on external devices when going into suspend mode or recovering from suspend mode CMOS output; 8 mA drive DGND DGND B9 B8, G7 digital ground ground supply; down bonded to the exposed die pad (heat sink); to be connected to DGND during the PCB layout exposed die J9 pad [1] [2] [3] [4] [5] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals. All outputs and I/O pins can source 4 mA, unless otherwise specified. Control signals are not 3-stated. Add a decoupling capacitor (0.1 F) to all the supply pins. For better EMI results, add a 0.01 F capacitor in parallel to 0.1 F. The DMA bus is in 3-state until a DMA command (see Section 9.4.1) is executed. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 11 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8. Functional description The ISP1583 is a high-speed USB peripheral controller. It implements the Hi-Speed USB or the Original USB physical layer, and the packet protocol layer. It concurrently maintains up to 16 USB endpoints (control IN, control OUT, and seven IN and seven OUT configurable) along with endpoint EP0 set up, which accesses the set-up buffer. The Ref. 1 "Universal Serial Bus Specification Rev. 2.0", Chapter 9 protocol handling is executed using the external firmware. The ISP1583 has a fast general-purpose interface to communicate with most types of microcontrollers and microprocessors. This microcontroller interface is configured using pins BUS_CONF/DA0, MODE1 and MODE0/DA1 to accommodate most interface types. Two bus configurations are available, selected using input BUS_CONF/DA0 during power-up: * Generic processor mode (pin BUS_CONF/DA0 = HIGH): - AD[7:0]: 8-bit address bus (selects target register) - DATA[15:0]: 16-bit data bus (shared by processor and DMA) - Control signals: RW_N and DS_N or RD_N and WR_N (selected using pin MODE0/DA1), CS_N - DMA interface (generic slave mode only): Uses lines DATA[15:0] as data bus, DIOR and DIOW as dedicated read and write strobes * Split bus mode (pin BUS_CONF/DA0 = LOW): - AD[7:0]: 8-bit local microprocessor bus (multiplexed address and data) - DATA[15:0]: 16-bit DMA data bus - Control signals: CS_N, ALE or A0 (selected using pin MODE1), RW_N and DS_N or RD_N and WR_N (selected using pin MODE0/DA1) - DMA interface (master or slave mode): Uses DIOR and DIOW as dedicated read and write strobes For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer data to or from external memory or devices. The DMA interface can be configured by writing to proper DMA registers (see Section 9.4). The ISP1583 supports Hi-Speed USB and Original USB signaling. The USB signaling speed is automatically detected. The ISP1583 has 8 kB of internal FIFO memory, which is shared among enabled USB endpoints, including control IN and control OUT endpoints, and set-up token buffer. There are seven IN and seven OUT configurable endpoints, and two fixed control endpoints that are 64 bytes long. Any of the seven IN and seven OUT endpoints can be separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually configured, depending on the requirements of the application. Optional double buffering increases the data throughput of these data endpoints. The ISP1583 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an internal 1.8 V regulator to power the digital logic. The I/O voltage can range from 1.65 V to 3.6 V. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 12 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Endpoint access and programmability Maximum packet size 8 bytes (fixed) 64 bytes (fixed) 64 bytes (fixed) programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable Double buffering Endpoint type no no no yes yes yes yes yes yes yes yes yes yes yes yes yes yes set-up token control OUT control IN programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable Direction OUT OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN Table 4. Endpoint identifier EP0SETUP EP0RX EP0TX EP1RX EP1TX EP2RX EP2TX EP3RX EP3TX EP4RX EP4TX EP5RX EP5TX EP6RX EP6TX EP7RX EP7TX The ISP1583 operates on a 12 MHz crystal oscillator. An integrated 40 x PLL clock multiplier generates the internal sampling clock of 480 MHz. 8.1 DMA interface, DMA handler and DMA registers The DMA block can be subdivided into two blocks: DMA handler and DMA interface. The firmware writes to the DMA Command register to start a DMA transfer (see Table 51). The command opcode determines whether a generic DMA, Parallel I/O (PIO) or Multi-word DMA (MDMA) transfer will start. The handler interfaces to the same FIFO (internal RAM) as used by the USB core. On receiving the DMA command, the DMA handler directs the data from the endpoint FIFO to the external DMA device or from the external DMA device to the endpoint FIFO. The DMA interface configures the timing and the DMA handshake. Data can be transferred using either the DIOR and DIOW strobes or the DACK and DREQ handshakes. DMA configurations are set up by writing to the DMA Configuration register (see Table 56 and Table 57). For an IDE-based storage interface, applicable DMA modes are PIO and MDMA (Multi-word DMA; ATA). For a generic DMA interface, DMA modes that can be used are Generic DMA (GDMA) slave. Remark: The DMA endpoint buffer length must be a multiple of 4 bytes. For details on DMA registers, see Section 9.4. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 13 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.2 Hi-Speed USB transceiver The analog transceiver directly interfaces to the USB cable through integrated termination resistors. The high-speed transceiver requires an external resistor (12.0 k 1 %) between pin RREF and ground to ensure an accurate current mirror that generates the Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the ISP1583 compliant to Hi-Speed USB and Original USB, supporting both the high-speed and full-speed physical layers. After automatic speed detection, the NXP Serial Interface Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling. 8.3 MMU and integrated RAM The Memory Management Unit (MMU) manages the access to the integrated RAM that is shared by the USB, microcontroller handler and DMA handler. Data from the USB bus is stored in the integrated RAM, which is cleared only when the microcontroller has read the corresponding endpoint, or the DMA controller has written all data from the RAM of the corresponding endpoint to the DMA bus. The OUT endpoint buffer can also be forcibly cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is available for buffering. 8.4 Microcontroller interface and microcontroller handler The microcontroller interface allows direct interfacing to most microcontrollers and microprocessors. The interface is configured at power-up through pins BUS_CONF/DA0, MODE1 and MODE0/DA1. When pin BUS_CONF/DA0 = HIGH, the microcontroller interface switches to generic processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0] is the separate 16-bit data bus. If pin BUS_CONF/DA0 = LOW, the interface is in split bus mode, where AD[7:0] is the local microprocessor bus (multiplexed address and data) and DATA[15:0] is solely used as the DMA bus. When pin MODE0/DA1 = HIGH, pins RW_N/RD_N and DS_N/WR_N are the read and write strobes (8051 mode). If pin MODE0/DA1 = LOW, pins RW_N/RD_N and DS_N/WR_N represent the direction and data strobes (Freescale mode). When pin MODE1 = LOW, pin ALE/A0 is used to latch the multiplexed address on pins AD[7:0]. When pin MODE1 = HIGH, pin ALE/A0 is used to indicate address or data. Pin MODE1 is only used in split bus mode; in generic processor mode, it must be tied to VCC(I/O). The microcontroller handler allows the external microcontroller to access the register set in the NXP SIE, as well as the DMA handler. The initialization of the DMA configuration is done through the microcontroller handler. 8.5 OTG SRP module The OTG supplement defines a Session Request Protocol (SRP), which allows a B-device to request the A-device to turn on VBUS and start a session. This protocol allows the A-device, which may be battery-powered, to conserve power by turning off VBUS when there is no bus activity while still providing a means for the B-device to initiate bus activity. Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including a standard USB peripheral, can initiate SRP. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 14 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller The ISP1583 is a device that can initiate SRP. 8.6 NXP high-speed transceiver 8.6.1 NXP Parallel Interface Engine (PIE) In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel bidirectional data interface. The functions of the HS module also include bit-stuffing or de-stuffing and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic. 8.6.2 Peripheral circuit To maintain a constant current driver for HS transmit circuits and to bias other analog circuits, an internal band gap reference circuit and an RREF resistor form the reference current. This circuit requires an external precision resistor (12.0 k 1 %) connected to the analog ground. 8.6.3 HS detection The ISP1583 handles more than one electrical state, Full-Speed (FS) or High-Speed (HS), under the USB specification. When the USB cable is connected from the peripheral to the host controller, the ISP1583 defaults to the FS state, until it sees a bus reset from the host controller. During the bus reset, the peripheral initiates an HS chirp to detect whether the host controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there is an HS host connected, then the ISP1583 switches to the HS state. In the HS state, the ISP1583 must observe the bus for periodic activity. If the bus remains inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero (SE0) condition on the USB bus. If an SE0 condition is detected for the designated time (100 s to 875 s; refer to Ref. 1 "Universal Serial Bus Specification Rev. 2.0", Section 7.1.7.6), the ISP1583 switches to the HS chirp state to perform an HS detection handshake. Otherwise, the ISP1583 remains in the FS state, adhering to the bus-suspend specification. 8.6.4 Isolation Ensure that the DP and DM lines are maintained in a clean state, without any residual voltage or glitches. Once the ISP1583 is reset and the clock is available, ensure that there are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines. Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1583 DP and DM lines, there is a possibility of the ISP1583 clocking this state into the internal core, causing unknown behaviors. 8.7 NXP Serial Interface Engine (SIE) The NXP SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel or serial conversion, bit-stuffing or de-stuffing, CRC checking or generation, Packet IDentifier (PID) verification or generation, address recognition, handshake evaluation or generation. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 15 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.8 SoftConnect The USB connection is established by pulling pin DP (for full-speed devices) to HIGH through a 1.5 k pull-up resistor. In the ISP1583, an external 1.5 k pull-up resistor must be connected between pin RPU and 3.3 V. The RPU pin connects the pull-up resistor to pin DP, when bit SOFTCT in the Mode register is set (see Table 24 and Table 25). After a hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT = 0). The USB bus reset does not change the value of bit SOFTCT. When VBUS is not present, the SOFTCT bit must be set to logic 0 to comply with the back-drive voltage. 8.9 Reconfiguring endpoints The ISP1583 endpoints have a limitation when implementing a composite device with at least two functionalities that require the support of alternate settings, for example, the video class and audio class devices. The ISP1583 endpoints cannot be reconfigured on the fly because it is implemented as a FIFO base. The internal RAM partition will be corrupted if there is a need to reconfigure endpoints on the fly because of alternate settings request, causing data corruption. For details and work-around, refer to Ref. 3 "Using ISP1582/3 in a composite device application with alternate settings (AN10071)". 8.10 System controller The system controller implements the USB power-down capabilities of the ISP1583. Registers are protected against data corruption during wake-up following a resume (from the suspend state) by locking the write access, until an unlock code is written to the Unlock Device register (see Table 90 and Table 91). 8.11 Modes of operation The ISP1583 has two bus configuration modes, selected using pin BUS_CONF/DA0 at power-up: * Split bus mode (BUS_CONF/DA0 = LOW): 8-bit multiplexed address and data bus, and separate 8-bit or 16-bit DMA bus * Generic processor mode (BUS_CONF/DA0 = HIGH): separate 8-bit address and 16-bit data bus Details of bus configurations for each mode are given in Table 5. Typical interface circuits for each mode are given in Section 14. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 16 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 5. Bus configuration modes DMA width WIDTH = 0 D[7:0] WIDTH = 1 D[15:0] split bus mode: Description Pin PIO width BUS_CONF/ DA0 LOW AD[7:0] * * HIGH A[7:0] and D[15:0] D[7:0] D[15:0] Multiplexed address and data on pins AD[7:0] Separate 8-bit or 16-bit DMA bus on pins DATA[15:0] Separate 8-bit address on pins AD[7:0] 16-bit data (PIO and DMA) on pins DATA[15:0] generic processor mode: * * 8.12 Pins status Table 6 illustrates the behavior of ISP1583 pins with VCC(I/O) and VCC(3V3) in various operating conditions. Table 6. VCC(3V3) 0V 0V 3.3 V 3.3 V ISP1583 pin status VCC(I/O) 0V 1.65 V to 3.6 V 1.65 V to 3.6 V 1.65 V to 3.6 V State dead[1] plug-out[2] plug-in[3] reset after reset Pin Input unknown high-Z high-Z state depends on how the pin is driven state depends on how the pin is driven Output unknown unknown unknown output output I/O unknown high-Z high-Z high-Z state depends on how the pin is configured 0 V 3.3 V 1.65 V to 3.6 V [1] [2] [3] Dead: the USB cable is plugged out, and VCC(I/O) is not available. Plug-out: the USB cable is not present, but VCC(I/O) is available. Plug-in: the USB cable is being plugged in, and VCC(I/O) is available. Table 7 illustrates the behavior of output pins with VCC(I/O) and VCC(3V3) in various operating conditions. Table 7. VCC(3V3) 0V 0V 0 V 3.3 V 3.3 V 3.3 V [1] [2] [3] ISP1583 output pin status VCC(I/O) 0V 1.65 V to 3.6 V 1.65 V to 3.6 V 1.65 V to 3.6 V 1.65 V to 3.6 V State dead[1] plug-out[2] plug-in[3] reset after reset INT LOW LOW LOW HIGH HIGH SUSPEND HIGH HIGH HIGH LOW LOW Dead: the USB cable is plugged out, and VCC(I/O) is not available. Plug-out: the USB cable is not present, but VCC(I/O) is available. Plug-in: the USB cable is being plugged in, and VCC(I/O) is available. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 17 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.13 Interrupt 8.13.1 Interrupt output pin The Interrupt Configuration register of the ISP1583 controls the behavior of the INT output pin. The polarity and signaling mode of the INT pin can be programmed by setting bits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see Table 28. Bit GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT; see Table 25. Default settings after reset are active LOW and level mode. When pulse mode is selected, a pulse of 60 ns is generated when the OR-ed combination of all interrupt bits changes from logic 0 to logic 1. Figure 5 shows the relationship between interrupt events and pin INT. Each of the indicated USB and DMA events is logged in a status bit of the Interrupt register and the DMA Interrupt Reason register, respectively. Corresponding bits in the Interrupt Enable register and the DMA Interrupt Enable register determine whether an event will generate an interrupt. Interrupts can be masked globally by means of bit GLINTENA of the Mode register. Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation of INT signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt Configuration register controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the Interrupt Configuration register controls the generation of INT signals for the OUT pipe; see Table 29. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 18 of 99 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 07 -- 22 September 2008 (c) NXP B.V. 2008. All rights reserved. ISP1583_7 NXP Semiconductors DMA Interrupt Reason register GDMA_STOP Interrupt Enable register IEBRST EXT_EOT INT_EOT IESOF .... ...... IEDMA ...... BSY_DONE TF_RD_DONE CMD_INTRQ_OK .............. OR .... IEP7RX IEP7TX OR Interrupt register BRESET SOF DMA Interrupt Enable register IE_GDMA_STOP IE_EXT_EOT ...... .... IE_INT_EOT LE Hi-Speed USB peripheral controller ...... DMA LATCH Interrupt Configuration register INTPOL INT IE_BSY_DONE IE_TF_RD_DONE IE_CMD_INTRQ_OK PULSE OR LEVEL GENERATOR EP7RX EP7TX ...... GLINTENA Mode register 004aaa267 ISP1583 19 of 99 Fig 5. Interrupt logic NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.13.2 Interrupt control Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior of this bit is given in Figure 6. The following illustrations are only applicable for level trigger. Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in the corresponding Interrupt register bit. Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in the Interrupt register is already set. Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The bold line shows the desired behavior of pin INT. Deassertion of pin INT can be achieved either by clearing all the bits in the Interrupt register or the DMA Interrupt Reason register, depending on the event. Remark: When clearing an interrupt event, perform write to all the bytes of the register. For more information on interrupt control, see Section 9.2.2, Section 9.2.5 and Section 9.5.1. A INT pin B C GLINTENA = 0 (during this time, an interrupt event occurs, for example, SOF asserted) GLINTENA = 1 SOF asserted GLINTENA = 0 SOF asserted 004aaa394 Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled). Fig 6. Behavior of bit GLINTENA 8.14 VBUS sensing The VBUS pin is one of the ways to wake up the clock when the ISP1583 is suspended with bit CLKAON set to logic 0 (clock off option). To detect whether the host is connected or not, that is VBUS sensing, a 1 M resistor and a 1 F electrolytic or tantalum capacitor must be added to damp the overshoot on plug in. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 20 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 55 ISP1583 1 M 1 F USB CONNECTOR 004aaa449 The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see Table 3. Fig 7. Resistor and electrolytic or tantalum capacitor needed for VBUS sensing 001aaf440 Fig 8. Oscilloscope reading: no resistor and capacitor in the network 001aaf441 Fig 9. Oscilloscope reading: with resistor and capacitor in the network ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 21 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.15 Power-on reset The ISP1583 requires a minimum pulse width of 500 s. The RESET_N pin can either be connected to VCC(3V3) (using the internal POR circuit) or externally controlled (by the microcontroller, ASIC, and so on). When VCC(3V3) is directly connected to the RESET_N pin, internal pulse width tPORP will typically be 200 ns. The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5 on the VCC(POR) curve (Figure 10). t0 -- The internal POR starts with a HIGH level. t1 -- The detector will see the passing of the trip level and a delay element will add another tPORP before it drops to LOW. t2 to t3 -- The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip for more than 11 s. t4 to t5 -- The dip is too short (< 11 s) and the internal POR pulse will not react and will remain LOW. VCC(POR) Vtrip t0 t1 t2 t3 t4 t5 PORP(1) 004aab162 tPORP tPORP (1) PORP = Power-On Reset Pulse. Fig 10. POR timing Figure 11 shows the availability of the clock with respect to the external POR. VCC(3V3) 500 s external clock 2 ms RESET_N A B C 004aaa906 Power on VCC(3V3) at A. Stable external clock is to be available at B. The ISP1583 is operational at C. Fig 11. Clock with respect to the external POR ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 22 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.16 Power supply The ISP1583 can be powered by 3.3 V 0.3 V, and from 1.65 V to 3.6 V at the interface. For details, see Figure 12. If the ISP1583 is powered by VCC(3V3) = 3.3 V, an integrated 3.3 V-to-1.8 V voltage regulator provides a 1.8 V supply voltage for the internal logic. In sharing mode (that is, when VCC(3V3) is not present and VCC(I/O) is present), all I/O pins are input type, the interrupt pin is connected to ground, and the suspend pin is connected to VCC(I/O). See Table 7. 61 VCC(3V3) 0.01 F 3.3 V 0.3 V 0.1 F 26 VCC(I/O) 0.01 F 1.65 V to 3.6 V 0.1 F 41 VCC(I/O) 0.01 F 0.1 F ISP1583 54 VCC(I/O) 0.01 F 0.1 F 56 VCC1V8 4.7 F(1) 0.1 F 32 VCC1V8 0.1 F 004aaa271 (1) At the VCC input (3.3 V) to the USB controller, if the ripple voltage is less than 20 mV, then 4.7 F standard electrolytic or tantalum capacitors (tested ESR up to 10 ) should be OK at the VCC1V8 output. If the ripple voltage at the input is higher than 20 mV, then use 4.7 F LOW ESR capacitors (ESR from 0.2 to 2 ) at the VCC1V8 output. This is to improve the high-speed signal quality at the USB side. The figure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2 ballouts, see Table 3. Fig 12. ISP1583 with a 3.3 V supply Table 8 shows power modes in which the ISP1583 can be operated. Table 8. VCC(3V3) VBUS [1] Power modes VCC(I/O) VBUS [2] Power mode bus-powered self-powered power-sharing (hybrid) System-powered VBUS[1] [1] [2] ISP1583_7 system-powered system-powered The power supply to the IC (VCC(3V3)) is 3.3 V. Therefore, if the application is bus-powered, a 3.3 V regulator needs to be used. VCC(I/O) can range from 1.65 V to 3.6 V. If the application is bus-powered, a voltage regulator must be used. (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 23 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.16.1 Power-sharing mode to GPIO of processor for sensing VBUS 5 V-to-3.3 V VOLTAGE REGULATOR 1.5 k RPU VCC(3V3) VBUS VBUS USB ISP1583 1 F 1 M VCC(I/O) 004aaa458 VCC(I/O) is system powered. Fig 13. Power-sharing mode As can be seen in Figure 13, in power-sharing mode, VCC(3V3) is supplied by the output of the 5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. VCC(I/O) is supplied through the power source of the system. When the USB cable is plugged in, the ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled. The processor will experience continuous interrupt because the default status of the interrupt pin when operating in sharing mode with VBUS not present is LOW. To overcome this, implement external VBUS sensing circuitry. The output from the voltage regulator can be connected to pin GPIO of the processor to qualify the interrupt from the ISP1583. Remark: When the core power is applied, the ISP1583 must be reset using the RESET_N pin. The minimum width of the reset pulse width must be 2 ms. VCC(I/O) VCC(3V3) INT power off power off 004aaa459 Fig 14. Interrupt pin status during power off in power-sharing mode ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 24 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Operation truth table for SoftConnect Power supply VCC(3V3) VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V Bit SOFTCT in Mode register enabled not applicable Table 9. ISP1583 operation Normal bus operation Core power is lost Table 10. 3.3 V 0V Operation truth table for clock off during suspend Power supply VCC(3V3) VCC(I/O) 3.3 V RPU (3.3 V) 3.3 V VBUS 5V Clock off during suspend enabled ISP1583 operation Clock will wake up: After a resume and After a bus reset Core power is lost Table 11. 3.3 V 0V 3.3 V 0V 0V not applicable Operation truth table for back voltage compliance Power supply VCC(3V3) VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V Bit SOFTCT in Mode register enabled not applicable ISP1583 operation Back voltage is not measured in this mode Back voltage is not an issue because core power is lost Table 12. 3.3 V 0V Operation truth table for OTG Power supply VCC(3V3) VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V not applicable not applicable OTG register ISP1583 operation SRP is not applicable 3.3 V OTG is not possible because VBUS is not 0 V present and so core power is lost ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 25 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 8.16.2 Self-powered mode 1.5 k RPU VCC(3V3) VBUS VBUS USB ISP1583 1 F 1 M VCC(I/O) 004aaa461 VCC(I/O) and VCC(3V3) are system powered. Fig 15. Self-powered mode In self-powered mode, VCC(3V3) and VCC(I/O) are supplied by the system. See Figure 15. Table 13. Operation truth table for SoftConnect Power supply VCC(3V3) Normal bus operation No pull up on DP [1] ISP1583 operation VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 3.3 V VBUS 5V 0 V[1] Bit SOFTCT in Mode register enabled disabled 3.3 V 3.3 V When the USB cable is removed, SoftConnect is disabled. Table 14. Operation truth table for clock off during suspend Power supply VCC(3V3) VCC(I/O) 3.3 V RPU (3.3 V) 3.3 V VBUS 5V Clock off during suspend enabled ISP1583 operation Clock will wake up: After a resume and After a bus reset Clock will wake up: After detecting the presence of VBUS Table 15. 3.3 V 3.3 V 3.3 V 3.3 V 0V5V enabled Operation truth table for back voltage compliance Power supply VCC(3V3) VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 3.3 V VBUS 5V 0V Bit SOFTCT in Mode register enabled disabled ISP1583 operation Back voltage is not measured in this mode 3.3 V Back voltage is not an issue because pull 3.3 V up on DP will not be present when VBUS is not present ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 26 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Operation truth table for OTG Power supply VCC(3V3) VCC(I/O) 3.3 V 3.3 V RPU (3.3 V) 3.3 V 3.3 V VBUS 5V 0V not applicable operational OTG register Table 16. ISP1583 operation SRP is not applicable SRP is possible 3.3 V 3.3 V 8.16.3 Bus-powered mode 5 V-to-3.3 V VOLTAGE REGULATOR VBUS VCC(3V3) VBUS USB 1.65 V to 3.6 V ISP1583 VCC(I/O) 1.5 k 1 F 1 M RPU 004aaa463 VCC(I/O) is powered by VBUS. Fig 16. Bus-powered mode In bus-powered mode (see Figure 16), VCC(3V3) and VCC(I/O) are supplied by the output of the 5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. On plugging the USB cable, the ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled. Table 17. Operation truth table for SoftConnect Power supply VCC(3V3) Normal bus operation Power is lost Table 18. 3.3 V 0V VCC(I/O) 3.3 V 0V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V Bit SOFTCT in Mode register enabled not applicable ISP1583 operation Operation truth table for clock off during suspend Power supply VCC(3V3) VCC(I/O) 3.3 V RPU (3.3 V) 3.3 V VBUS 5V Clock off during suspend enabled ISP1583 operation Clock will wake up: After a resume and After a bus reset Power is lost 3.3 V 0V 0V 0V 0V not applicable ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 27 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Operation truth table for back voltage compliance Power supply VCC(3V3) VCC(I/O) 3.3 V 0V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V Bit SOFTCT in Mode register enabled not applicable Table 19. ISP1583 operation Back voltage is not measured in this mode Power is lost Table 20. 3.3 V 0V Operation truth table for OTG Power supply VCC(3V3) VCC(I/O) 3.3 V 0V RPU (3.3 V) 3.3 V 0V VBUS 5V 0V not applicable not applicable OTG register ISP1583 operation SRP is not applicable Power is lost 3.3 V 0V ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 28 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 9. Register description Table 21. Name Initialization registers Address Mode Interrupt Configuration OTG Interrupt Enable Data flow registers Endpoint Index Control Function Data Port Buffer Length Buffer Status Endpoint MaxPacketSize Endpoint Type DMA registers DMA Command DMA Transfer Counter DMA Configuration DMA controller DMA controller DMA controller 30h 34h 38h controls all DMA transfers sets byte count for DMA transfer byte 0: sets GDMA configuration (counter enable, data strobing, bus width) 1 4 1 Section 9.4.1 on page 47 Section 9.4.2 on page 49 Section 9.4.3 on page 50 endpoints endpoint endpoint endpoint endpoint endpoint endpoint 2Ch 28h 20h 1Ch 1Eh 04h 08h endpoint selection, data flow direction 1 endpoint buffer management data access to endpoint FIFO packet size counter buffer status for each endpoint maximum packet size selects endpoint type: isochronous, bulk or interrupt 1 2 2 1 2 2 Section 9.3.1 on page 38 Section 9.3.2 on page 39 Section 9.3.3 on page 40 Section 9.3.4 on page 41 Section 9.3.5 on page 42 Section 9.3.6 on page 43 Section 9.3.7 on page 44 device device device device device 00h 0Ch 10h 12h 14h USB device address and enable power-down options, global interrupt enable, SoftConnect interrupt sources, trigger mode, output polarity OTG implementation interrupt source enabling 1 2 1 1 4 Section 9.2.1 on page 31 Section 9.2.2 on page 31 Section 9.2.3 on page 33 Section 9.2.4 on page 34 Section 9.2.5 on page 36 Register overview Destination Address Description Size (bytes) Reference 39h byte 1: sets ATA configuration (IORDY 1 enable, mode selection: ATA, MDMA, PIO) endian type, master or slave selection, signal polarity for DACK, DREQ, DIOW, DIOR, EOT 1 Section 9.4.4 on page 52 DMA Hardware DMA controller 3Ch ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 29 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 21. Name Register overview ...continued Destination ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral DMA controller DMA controller DMA controller DMA controller DMA controller Address Description 40h 48h 49h 4Ah 4Bh 4Ch 4Dh 44h 4Eh 4Fh 50h 54h 58h 60h 64h single address word register: byte 0 (lower byte) is accessed first IDE device access IDE device access IDE device access IDE device access IDE device access IDE device access Size (bytes) 2 1 1 1 1 1 1 Reference Section 9.4.5 on page 53 Task File 1F0 Task File 1F1 Task File 1F2 Task File 1F3 Task File 1F4 Task File 1F5 Task File 1F6 Task File 1F7 Task File 3F6 Task File 3F7 DMA Interrupt Reason DMA Interrupt Enable DMA Endpoint DMA Strobe Timing DMA Burst Counter General registers Interrupt Chip ID Frame Number IDE device access (write only; reading 1 returns FFh) IDE device access IDE device access shows reason (source) for DMA interrupt enables DMA interrupt sources selects endpoint FIFO, data flow direction strobe duration in MDMA mode DMA burst length 1 1 2 2 1 1 2 Section 9.4.6 on page 56 Section 9.4.7 on page 57 Section 9.4.8 on page 57 Section 9.4.9 on page 58 Section 9.4.10 on page 59 Section 9.5.1 on page 59 Section 9.5.2 on page 61 Section 9.5.3 on page 62 Section 9.5.4 on page 62 Section 9.5.5 on page 63 Section 9.5.6 on page 63 device device device 18h 70h 74h shows interrupt sources 4 product ID code and hardware version 3 last successfully received Start-Of-Frame: lower byte (byte 0) is accessed first allows save or restore of firmware status during suspend re-enables register write access after suspend 2 Scratch Unlock Device Test Mode device device PHY 78h 7Ch 84h 2 2 direct setting of the DP and DM 1 states, internal transceiver test (PHY) 9.1 Register access Register access depends on the bus width used: * 8-bit bus: multi-byte registers are accessed lower byte (LSByte) first * 16-bit bus: for single-byte registers, the upper byte (MSByte) must be ignored Endpoint specific registers are indexed using the Endpoint Index register. The target endpoint must be selected before accessing the following registers: ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 30 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller * * * * * * Buffer Length Buffer Status Control Function Data Port Endpoint MaxPacketSize Endpoint Type Remark: Write zero to all reserved bits, unless otherwise specified. 9.2 Initialization registers 9.2.1 Address register (address: 00h) This register sets the USB assigned address and enables the USB device. Table 22 shows the Address register bit allocation. Bits DEVADDR[6:0] will be cleared whenever a bus reset, a power-on reset or a soft reset occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs. In response to standard USB request SET_ADDRESS, the firmware must write the (enabled) device address to the Address register, followed by sending an empty packet to the host. The new device address is activated when the device receives an acknowledgment from the host for the empty packet token. Table 22. Bit Symbol Reset Bus reset Access Address register: bit allocation 7 DEVEN 0 unchanged R/W 0 0 R/W Table 23. Bit 7 6 to 0 0 0 R/W 0 0 R/W 6 5 4 3 DEVADDR[6:0] 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 2 1 0 Address register: bit description Symbol DEVEN DEVADDR[6:0] Description Device Enable: Logic 1 enables the device. The device will not respond to the host, unless this bit is set. Device Address: This field specifies the USB device address. 9.2.2 Mode register (address: 0Ch) This register consists of 2 bytes (bit allocation: see Table 24). The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset, clock signals and SoftConnect operation. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 31 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 24. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access [1] Mode register: bit allocation 15 TEST2 R 7 CLKAON 0 unchanged R/W 14 TEST1 R 6 SNDRSU 0 0 R/W 13 TEST0 R 5 GOSUSP 0 0 R/W 4 SFRESET 0 0 R/W 12 11 reserved 3 GLINTENA 0 unchanged R/W 2 WKUPCS 0 0 R/W 10 9 DMA CLKON 0 0 R/W 1 PWRON 0 unchanged R/W 8 VBUSSTAT -[1] -[1] R 0 SOFTCT 0 unchanged R/W Value depends on the status of the VBUS pin. Table 25. Bit 15 14 13 9 Mode register: bit description Symbol TEST2 TEST1 TEST0 DMACLKON Description This bit reflects the MODE1 pin setting. Only for test purposes. This bit reflects the MODE0/DA1 pin setting. Only for test purposes. This bit reflects the BUS_CONF/DA0 pin setting. Only for test purposes. reserved DMA Clock On: 0 -- Power save mode; the DMA circuit will stop completely to save power. 1 -- Supply clock to the DMA circuit. 12 to 10 - 8 7 VBUSSTAT CLKAON VBUS Pin Status: This bit reflects the VBUS pin status. Clock Always On: Logic 1 indicates that internal clocks are always running when in the suspend state. Logic 0 switches off the internal oscillator and PLL when the device goes into suspend mode. The device will consume less power if this bit is set to logic 0. The clock is stopped about 2 ms after bit GOSUSP is set and then cleared. Send Resume: Writing logic 1, followed by logic 0 will generate a 10 ms upstream resume signal. Remark: The upstream resume signal is generated 5 ms after this bit is set to logic 0. 6 SNDRSU 5 4 GOSUSP SFRESET Go Suspend: Writing logic 1, followed by logic 0 will activate suspend mode. Soft Reset: Writing logic 1, followed by logic 0 will enable a software-initiated reset to the ISP1583. A soft reset is similar to a hardware-initiated reset (using the RESET_N pin). ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 32 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Mode register: bit description ...continued Symbol GLINTENA Description Global Interrupt Enable: Logic 1 enables all interrupts. Individual interrupts can be masked by clearing the corresponding bits in the Interrupt Enable register. When this bit is not set, an unmasked interrupt will not generate an interrupt trigger on the interrupt pin. If global interrupt, however, is enabled while there is any pending unmasked interrupt, an interrupt signal will be immediately generated on the interrupt pin. (If the interrupt is set to pulse mode, the interrupt events that were generated before the global interrupt is enabled will not appear on the interrupt pin.) Table 25. Bit 3 2 WKUPCS Wake-up on Chip selection: Logic 1 enables wake-up from suspend mode through a valid register read on the ISP1583. (A read will invoke the chip clock to restart. If you write to the register before the clock gets stable, it may cause malfunctioning.) Power On: The SUSPEND pin output control. 0 -- The SUSPEND pin is HIGH when the ISP1583 is in the suspend state. Otherwise, the SUSPEND pin is LOW. 1 -- When the device is woken up from the suspend state, there will be a 1 ms active HIGH pulse on the SUSPEND pin. The SUSPEND pin will remain LOW in all other states. 1 PWRON 0 SOFTCT SoftConnect: Logic 1 enables the connection of the 1.5 k pull-up resistor on pin RPU to the DP pin. The status of the chip is shown in Table 26. Table 26. Bus state VBUS on Status of the chip SoftConnect = on pull-up resistor on pin DP SoftConnect = off pull-up resistor on pin DP is removed; suspend interrupt is generated after 3 ms of no bus activity VBUS off pull-up resistor on pin DP is present; pull-up resistor on pin DP is removed; suspend interrupt is generated after suspend interrupt is generated after 3 ms of 3 ms of no bus activity no bus activity 9.2.3 Interrupt Configuration register (address: 10h) This 1-byte register determines the behavior and polarity of the INT output. The bit allocation is shown in Table 27. When the USB SIE receives or generates an ACK, NAK or NYET, it will generate interrupts, depending on three Debug mode fields. CDBGMOD[1:0] -- interrupts for control endpoint 0 DDBGMODIN[1:0] -- interrupts for DATA IN endpoints 1 to 7 DDBGMODOUT[1:0] -- interrupts for DATA OUT endpoints 1 to 7 The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you to individually configure when the ISP1583 sends an interrupt to the external microprocessor. Table 29 lists available combinations. Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering). ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 33 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 27. Bit Symbol Reset Bus reset Access Interrupt Configuration register: bit allocation 7 1 1 R/W 6 1 1 R/W Table 28. Bit 7 to 6 5 to 4 3 to 2 1 0 5 1 1 R/W 4 1 1 R/W 3 1 1 R/W 2 1 1 R/W 1 INTLVL 0 unchanged R/W 0 INTPOL 0 unchanged R/W CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] Interrupt Configuration register: bit description Symbol CDBGMOD[1:0] DDBGMODIN[1:0] INTLVL INTPOL Description Control Endpoint 0 Debug Mode: For values, see Table 29 Data Debug Mode IN: For values, see Table 29 Interrupt Level: Selects signaling mode on output INT (0 = level; 1 = pulsed). In pulsed mode, an interrupt produces a 60 ns pulse. Interrupt Polarity: Selects signal polarity on output INT (0 = active LOW, 1 = active HIGH). DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see Table 29 Table 29. Value 00h 01h 1Xh [1] Debug mode settings CDBGMOD interrupt on all ACK and NAK interrupt on all ACK interrupt on all ACK and first NAK[1] DDBGMODIN interrupt on all ACK and NAK interrupt on ACK interrupt on all ACK and first NAK[1] DDBGMODOUT interrupt on all ACK, NYET and NAK interrupt on ACK and NYET interrupt on all ACK, NYET and first NAK[1] First NAK: the first NAK on an IN or OUT token is generated after a set-up token and an ACK sequence. 9.2.4 OTG register (address: 12h) The bit allocation of the OTG register is given in Table 30. Table 30. Bit Symbol Reset Bus reset Access OTG register: bit allocation 7 reserved 6 5 DP 0 0 R/W 4 BSESSVALID R/W 3 INITCOND R/W 2 DISCV 0 0 R/W 1 VP 0 0 R/W 0 OTG 0 0 R/W ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 34 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller OTG register: bit description reserved Data Pulsing: Used for data-line pulsing to toggle DP to generate the required data-line pulsing signal. The default value of this bit is logic 0. This bit must be cleared when data-line pulsing is completed. B-Session Valid: The device can initiate another VBUS discharge sequence after data-line pulsing and VBUS pulsing, and before it clears this bit and detects a session valid. This bit is latched to logic 1 once VBUS exceeds the B-device session valid threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The ISP1583 continuously updates this bit to logic 1 when the B-session is valid. If the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1583). 0 -- It implies that SRP has failed. To proceed to a normal operation, the device can restart SRP, clear bit OTG or proceed to an error handling process. 1 -- It implies that the B-session is valid. The device clears bit OTG, goes into normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register. The OTG host has a maximum of 5 s before it responds to a session request. During this period, the ISP1583 may request to suspend. Therefore, the device firmware must wait for some time if it wishes to know the SRP result (success: if there is minimum response from the host within 5 s; failure: if there is no response from the host within 5 s). Table 31. Bit 7 to 6 5 DP Symbol Description[1] 4 BSESS VALID 3 INIT COND Initial Condition: Write logic 1 to clear this bit. Wait for more than 2 ms and check the bit status. If it reads logic 0, it means that VBUS remains lower than 0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP is violated. So, the device must abort SRP. The bit is set to logic 1 by the ISP1583 when initial conditions are not met, and only writing logic 1 clears the bit. (If initial conditions are not met after this bit has been cleared, it will be set again). Remark: This implementation does not cover the case if an initial SRP condition is violated when this bit is read and data-line pulsing is started. 2 DISCV Discharge VBUS: Set to logic 1 to discharge VBUS. The device discharges VBUS before starting a new SRP. The discharge can take as long as 30 ms for VBUS to be charged less than 0.8 V. This bit must be cleared (write logic 0) before a session end. VBUS Pulsing: Used for VBUS pulsing to toggle VP to generate the required VBUS pulsing signal. This bit must be set for more than 16 ms and must be cleared before 26 ms. On-The-Go: 1 -- Enables the OTG function. The VBUS sensing functionality will be disabled. 0 -- Normal operation. All OTG control bits will be masked. Status bits are undefined. 1 VP 0 OTG [1] No interrupt is designed for OTG. The VBUS interrupt, however, may assert as a side effect during the VBUS pulsing. When OTG is in progress, the VBUS interrupt may be set because VBUS is charged over the VBUS sensing threshold or the OTG host has turned on the VBUS supply to the device. Even if the VBUS interrupt is found during SRP, the device must complete data-line pulsing and VBUS pulsing before starting the B_SESSION_VALID detection. OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it must provide a switch circuit to supply power to the ISP1583 core during SRP. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 35 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 9.2.4.1 Session Request Protocol (SRP) The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by VBUS pulsing. The A-device can detect either data-line pulsing or VBUS pulsing. The ISP1583 can initiate the B-device SRP by performing the following steps: 1. Set the OTG bit to start SRP. 2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG register. 3. Start data-line pulsing: set bit DP of the OTG register to logic 1. 4. Wait for 5 ms to 10 ms. 5. Stop data-line pulsing: set bit DP of the OTG register to logic 0. 6. Start VBUS pulsing: set bit VP of the OTG register to logic 1. 7. Wait for 10 ms to 20 ms. 8. Stop VBUS pulsing: set bit VP of the OTG register to logic 0. 9. Discharge VBUS for about 30 ms: optional by using bit DISCV of the OTG register. 10. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG cleared. 11. Once bit BSESSVALID is detected, turn on the SOFTCT bit to start normal bus enumeration. The B-device must complete both data-line pulsing and VBUS pulsing within 100 ms. Remark: When disabling OTG, data-line pulsing bit DP and VBUS pulsing bit VP must be cleared by writing logic 0. 9.2.5 Interrupt Enable register (address: 14h) This register enables or disables individual interrupt sources. The interrupt for each endpoint can individually be controlled using the associated bits IEPnRX or IEPnTX, here n represents the endpoint number. All interrupts can be globally disabled using bit GLINTENA in the Mode register (see Table 24). An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the USB bus. The interrupt generation depends on Debug mode settings of bit fields CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0] in the Interrupt Configuration register. All data IN transactions use the Transmit buffers (TX), which are handled by bits DDBGMODIN[1:0]. All data OUT transactions go through the Receive buffers (RX), which are handled by bits DDBGMODOUT[1:0]. Transactions on control endpoint 0 (IN, OUT and SETUP) are handled by bits CDBGMOD[1:0]. Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up and high-speed status) can also be individually controlled. A bus reset disables all enabled interrupts, except bit IEBRST (bus reset), which remains logic 1. The Interrupt Enable register consists of 4 bytes. The bit allocation is given in Table 32. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 36 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 32. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Interrupt Enable register: bit allocation 31 23 IEP6TX 0 0 R/W 15 IEP2TX 0 0 R/W 7 IEVBUS 0 0 R/W 30 22 IEP6RX 0 0 R/W 14 IEP2RX 0 0 R/W 6 IEDMA 0 0 R/W Table 33. Bit 31 to 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 29 reserved 21 IEP5TX 0 0 R/W 13 IEP1TX 0 0 R/W 5 IEHS_STA 0 0 R/W 20 IEP5RX 0 0 R/W 12 IEP1RX 0 0 R/W 4 IERESM 0 0 R/W 19 IEP4TX 0 0 R/W 11 IEP0TX 0 0 R/W 3 IESUSP 0 0 R/W 18 IEP4RX 0 0 R/W 10 IEP0RX 0 0 R/W 2 IEPSOF 0 0 R/W 28 27 26 25 IEP7TX 0 0 R/W 17 IEP3TX 0 0 R/W 9 reserved 1 IESOF 0 0 R/W 24 IEP7RX 0 0 R/W 16 IEP3RX 0 0 R/W 8 IEP0SETUP 0 0 R/W 0 IEBRST 0 1 R/W Interrupt Enable register: bit description Symbol IEP7TX IEP7RX IEP6TX IEP6RX IEP5TX IEP5RX IEP4TX IEP4RX IEP3TX IEP3RX IEP2TX IEP2RX IEP1TX IEP1RX IEP0TX IEP0RX IEP0SETUP Description reserved Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from control IN endpoint 0. Logic 1 enables interrupt from control OUT endpoint 0. reserved Logic 1 enables interrupt for the set-up data received on endpoint 0. (c) NXP B.V. 2008. All rights reserved. ISP1583_7 Product data sheet Rev. 07 -- 22 September 2008 37 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Interrupt Enable register: bit description ...continued Symbol IEVBUS IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF IEBRST Description Logic 1 enables interrupt for VBUS sensing. Logic 1 enables interrupt on the DMA Interrupt Reason register change detection. Logic 1 enables interrupt on detecting a high-speed status change. Logic 1 enables interrupt on detecting a resume state. Logic 1 enables interrupt on detecting a suspend state. Logic 1 enables interrupt on detecting a pseudo SOF. Logic 1 enables interrupt on detecting an SOF. Logic 1 enables interrupt on detecting a bus reset. Table 33. Bit 7 6 5 4 3 2 1 0 9.3 Data flow registers 9.3.1 Endpoint Index register (address: 2Ch) The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte, and the bit allocation is shown in Table 34. The following registers are indexed: * * * * * * Buffer length Buffer status Control function Data port Endpoint MaxPacketSize Endpoint type For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the Endpoint Index register must first be written with 02h. Remark: The Endpoint Index register and the DMA Endpoint register must not point to the same endpoint, irrespective of IN and OUT. Remark: The delay time from the Write Endpoint Index register to the Read Data Port register must be at least 190 ns. Remark: The delay time from the Write Endpoint Index register to the Write Data Port register must be at least 100 ns. Table 34. Bit Symbol Reset Bus reset Access Endpoint Index register: bit allocation 7 reserved 6 5 EP0SETUP 1 unchanged R/W 0 0 R/W 4 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 DIR 0 0 R/W ENDPIDX[3:0] ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 38 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Endpoint Index register: bit description Symbol EP0SETUP Description reserved Endpoint 0 Setup: Selects the SETUP buffer for endpoint 0. 0 -- Data buffer 1 -- SETUP buffer Must be logic 0 for access to endpoints other than set-up token buffer. Table 35. Bit 7 to 6 5 4 to 1 ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of buffer length, buffer status, control function, data port, endpoint type and MaxPacketSize. DIR Direction: Sets the target endpoint as IN or OUT. 0 -- Target endpoint refers to OUT (RX) FIFO 1 -- Target endpoint refers to IN (TX) FIFO 0 Table 36. SETUP Addressing of endpoint buffers EP0SETUP 1 0 0 0 0 ENDPIDX 00h 00h 00h 0Xh 0Xh DIR 0 0 1 0 1 Buffer name Control OUT Control IN Data OUT Data IN 9.3.2 Control Function register (address: 28h) The Control Function register performs the buffer management on endpoints. It consists of 1 byte, and the bit configuration is given in Table 37. Register bits can stall, clear or validate any enabled endpoint. Before accessing this register, the Endpoint Index register must first be written to specify the target endpoint. Table 37. Bit Symbol Reset Bus reset Access Control Function register: bit allocation 7 6 reserved 5 4 CLBUF 0 0 R/W 3 VENDP 0 0 R/W 2 DSEN 0 0 W 1 STATUS 0 0 R/W 0 STALL 0 0 R/W ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 39 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Control Function register: bit description Description reserved. Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The RX buffer is automatically cleared once the endpoint is completely read. This bit is set only when it is necessary to forcefully clear the buffer. Remark: If using double buffer, to clear both the buffers issue the CLBUF command two times. For details on clearing buffers, refer to Ref. 5 "ISP1582/83 and ISP1761 clearing an IN buffer (AN10045)". Table 38. Bit 4 7 to 5 - Symbol CLBUF 3 VENDP Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint to send on the next IN token. In general, the endpoint is automatically validated when its FIFO byte count has reached endpoint MaxPacketSize. This bit is set only when it is necessary to validate the endpoint with the FIFO byte count, which is below endpoint MaxPacketSize. Remark: Use either bit VENDP or register Buffer Length to validate endpoint FIFO with FIFO bytes. 2 DSEN Data Stage Enable: This bit controls the response of the ISP1583 to a control transfer. After the completion of the set-up stage, firmware must determine whether a data stage is required. For control OUT, firmware will set this bit and the ISP1583 goes into the data stage. Otherwise, the ISP1583 will NAK the data stage transfer. For control IN, firmware will set this bit before writing data to the TX FIFO and validate the endpoint. If no data stage is required, firmware can immediately set the STATUS bit after the set-up stage. Remark: The DSEN bit is cleared once the OUT token is acknowledged by the device and the IN token is acknowledged by the PC host. This bit cannot be read back and reading this bit will return logic 0. 1 STATUS Status Acknowledge: Only applicable for control IN or OUT. This bit controls the generation of ACK or NAK during the status stage of a SETUP transfer. It is automatically cleared when the status stage is completed, or when a SETUP token is received. No interrupt signal will be generated. 0 -- Sends NAK 1 -- Sends an empty packet following the IN token (peripheral-to-host) or ACK following the OUT token (host-to-peripheral) Remark: The STATUS bit is cleared to zero once the zero-length packet is acknowledged by the device or the PC host. Remark: Data transfers preceding the status stage must first be fully completed before the STATUS bit can be set. 0 STALL Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for isochronous transfers. Remark: Stalling a data endpoint will confuse the Data Toggle bit about the stalled endpoint because the internal logic picks up from where it is stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in the Endpoint Type register) to reset the PID. 9.3.3 Data Port register (address: 20h) This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed endpoint. The bit allocation is shown in Table 39. Peripheral-to-host (IN endpoint): After each write action, an internal counter is auto incremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in the TX FIFO. When all bytes are written (FIFO byte count = endpoint MaxPacketSize), the ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 40 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller buffer is automatically validated. The data packet will then be sent on the next IN token. When it is necessary to validate the endpoint whose byte count is less than MaxPacketSize, it can be done using the Control Function register (bit VENDP) or the Buffer Length register. Remark: The buffer can automatically be validated by using the Buffer Length register (see Table 41). Host-to-peripheral (OUT endpoint): After each read action, an internal counter is auto decremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in the RX FIFO. When all bytes are read, buffer contents are automatically cleared. A new data packet can then be received on the next OUT token. Buffer contents can also be cleared using the Control Function register (bit CLBUF), when it is necessary to forcefully clear contents. Remark: The delay time from the Write Endpoint Index register to the Read Data Port register must be at least 190 ns. Remark: The delay time from the Write Endpoint Index register to the Write Data Port register must be at least 100 ns. Table 39. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W Table 40. Bit 15 to 8 7 to 0 0 0 R/W 0 0 R/W 7 0 0 R/W 6 0 0 R/W 5 Data Port register: bit allocation 15 14 13 12 0 0 R/W 4 0 0 R/W 11 0 0 R/W 3 0 0 R/W 10 0 0 R/W 2 0 0 R/W 9 0 0 R/W 1 0 0 R/W 8 0 0 R/W 0 0 0 R/W DATAPORT[15:8] DATAPORT[7:0] Data Port register: bit description Symbol DATAPORT[7:0] Description data (lower byte) DATAPORT[15:8] data (upper byte) 9.3.4 Buffer Length register (address: 1Ch) This register determines the current packet size (DATACOUNT) of the indexed endpoint FIFO. The bit allocation is given in Table 41. The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint MaxPacketSize register is written (see Table 45). A smaller value can be written when required. After a bus reset, the Buffer Length register is made zero. IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer Length register is not significant. This register is useful only when transferring data that is not a multiple of MaxPacketSize. The following two examples demonstrate the significance of the Buffer Length register. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 41 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register need not be filled. This is because the transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be automatically validated because the last packet is also of MaxPacketSize. Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register must be filled with 62 bytes just before the microprocessor writes the last packet of 62 bytes. This ensures that the last packet, which is a short packet of 62 bytes, is automatically validated. Use bit VENDP in the Control register if you are not using the Buffer Length register. This is applicable only to PIO mode access. OUT endpoint: The DATACOUNT value is automatically initialized to the number of data bytes sent by the host on each ACK. Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is output as the lower byte (LSByte). Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint. Table 41. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W Table 42. Bit 15 to 0 0 0 R/W 0 0 R/W 7 0 0 R/W 6 0 0 R/W 5 Buffer Length register: bit allocation 15 14 13 12 0 0 R/W 4 0 0 R/W 11 0 0 R/W 3 0 0 R/W 10 0 0 R/W 2 0 0 R/W 9 0 0 R/W 1 0 0 R/W 8 0 0 R/W 0 0 0 R/W DATACOUNT[15:8] DATACOUNT[7:0] Buffer Length register: bit description Symbol DATACOUNT[15:0] Description Data Count: Determines the current packet size of the indexed endpoint FIFO. 9.3.5 Buffer Status register (address: 1Eh) This register is accessed using index. The endpoint index must first be set before accessing this register for the corresponding endpoint. It reflects the status of the double buffered endpoint FIFO. Remark: This register is not applicable to the control endpoint. Remark: For endpoint IN data transfer, firmware must ensure a 200 ns delay between writing of the data packet and reading the Buffer Status register. For endpoint OUT data transfer, firmware must also ensure a 200 ns delay between receiving the endpoint interrupt and reading the Buffer Status register. For more information, refer to Ref. 3 "Using ISP1582/3 in a composite device application with alternate settings (AN10071)". ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 42 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 43 shows the bit allocation of the Buffer Status register. Table 43. Bit Symbol Reset Bus reset Access Table 44. Bit 7 to 2 1 to 0 BUF[1:0] Buffer Status register: bit allocation 7 6 5 reserved 4 3 2 1 BUF1 0 0 R 0 BUF0 0 0 R Buffer Status register: bit description Symbol Description reserved Buffer: 00 -- Buffers are not filled. 01 -- One of the buffers is filled. 10 -- One of the buffers is filled. 11 -- Both the buffers are filled. 9.3.6 Endpoint MaxPacketSize register (address: 04h) This register determines the maximum packet size for all endpoints, except set-up token buffer, control IN and control OUT. The register contains 2 bytes, and the bit allocation is given in Table 45. Each time the register is written, the Buffer Length register of the corresponding endpoint is re-initialized to the FFOSZ field value. Bits NTRANS control the number of transactions allowed in a single microframe (for high-speed isochronous and interrupt endpoints only). Table 45. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 7 Endpoint MaxPacketSize register: bit allocation 15 14 reserved 6 5 13 12 0 0 R/W 4 FFOSZ[7:0] 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 11 0 0 R/W 3 10 0 0 R/W 2 9 FFOSZ[10:8] 0 0 R/W 1 0 0 R/W 0 8 NTRANS[1:0] ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 43 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Endpoint MaxPacketSize register: bit description Symbol NTRANS[1:0] Description reserved Number of Transactions (HS mode only). 00 -- 1 packet per microframe 01 -- 2 packets per microframe 10 -- 3 packets per microframe 11 -- reserved These bits are applicable only for isochronous or interrupt transactions. Table 46. Bit 15 to 13 12 to 11 10 to 0 FFOSZ[10:0] FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint. Applies to both high-speed and full-speed operations. The ISP1583 supports all the transfers given in Ref. 1 "Universal Serial Bus Specification Rev. 2.0". Each programmable FIFO can be independently configured using its Endpoint MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN plus OUT), including set-up token buffer, control IN and control OUT, must not exceed 8192 bytes. 9.3.7 Endpoint Type register (address: 08h) This register sets the endpoint type of the indexed endpoint: isochronous, bulk or interrupt. It also serves to enable the endpoint and configure it for double buffering. Automatic generation of an empty packet for a zero-length TX buffer can be disabled using bit NOEMPKT. The register contains 2 bytes, and the bit allocation is shown in Table 47. Table 47. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 7 6 reserved 5 4 NOEMPKT 0 0 R/W Endpoint Type register: bit allocation 15 14 13 12 reserved 3 ENABLE 0 0 R/W 2 DBLBUF 0 0 R/W 1 0 0 R/W 0 0 0 R/W ENDPTYP[1:0] 11 10 9 8 ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 44 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Endpoint Type register: bit description Symbol NOEMPKT Description reserved No Empty Packet: Logic 0 causes the ISP1583 to return a null length packet for the IN token after the DMA IN transfer is complete. For ATA mode or the DMA IN transfer, which does not require a null length packet after DMA completion, set to logic 1 to disable the generation of the null length packet. Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint. The memory size is allocated as specified in the Endpoint MaxPacketSize register. Logic 0 disables the FIFO. Remark: Stalling a data endpoint will confuse the Data Toggle bit on the stalled endpoint because the internal logic picks up from where it has stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in the Endpoint Type register) to reset the PID. Table 48. Bit 15 to 5 4 3 ENABLE 2 DBLBUF Double Buffering: Logic 1 enables double buffering for the indexed endpoint. Logic 0 disables double buffering. Remark: When performing a write to two empty buffers, ensure that a minimum of 200 ns delay is provided from the last write of the first buffer to the first write of the second buffer. Otherwise, the first few data bytes may not be written to the second buffer, causing data corruption. 1 to 0 ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type. 00 -- not used 01 -- Isochronous 10 -- Bulk 11 -- Interrupt 9.4 DMA registers Two types of Generic DMA transfers and three types of IDE-specified transfers can be done by writing the proper opcode in the DMA Command register. Control bits are given in Table 49 (Generic DMA transfers) and Table 50 (IDE-specified transfers). GDMA read/write (opcode = 00h/01h) -- Generic DMA slave mode. Depending on the MODE[1:0] bits set in the DMA Configuration register, the DACK, DIOR or DIOW signal strobes data. These signals are driven by the external DMA controller. GDMA slave mode can operate in either counter mode or EOT-only mode. In counter mode, bit DIS_XFER_CNT in the DMA Configuration register must be set to logic 0. The DMA Transfer Counter register must be programmed before any DMA command is issued. The DMA transfer counter is set by writing from the LSByte to the MSByte (address: 34h to 37h). The DMA transfer count is internally updated only after the MSByte is written. Once the DMA transfer is started, the transfer counter starts decrementing and on reaching 0, bit DMA_XFER_OK is set and an interrupt is generated by the ISP1583. If the DMA master wishes to terminate the DMA transfer, it can issue an EOT signal to the ISP1583. This EOT signal overrides the transfer counter and can terminate the DMA transfer at any time. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 45 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer counter can still be programmed, it will not have any effect on the DMA transfer. The DMA transfer will start once the DMA command is issued. Any of the following three ways will terminate this DMA transfer: * Detecting an external EOT * Detecting an internal EOT (short packet on an OUT token) * Issuing a GDMA stop command There are three interrupts programmable to differentiate the method of DMA termination: bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register (see Table 74). MDMA (master) read/write (opcode = 06h/07h) -- Generic DMA master mode. Depending on the MODE[1:0] bits set in the DMA Configuration register, the DACK, DIOR or DIOW signal strobes data. These signals are driven by the ISP1583. In master mode, BURSTCOUNTER[12:0] in the DMA Burst Counter register, DIS_XFER_CNT in the DMA Configuration register and the external EOT signal are not applicable. The DMA transfer counter is always enabled and bit DMA_XFER_OK is set to 1 once the counter reaches 0. MDMA read/write (opcode = 06h/07h) -- Multi-word DMA mode for IDE transfers. The specification of this mode can be obtained from Ref. 4 "AT Attachment with Packet Interface Extension (ATA/ATAPI-4), ANSI INCITS 317-1998 (R2003)". DIOR and DIOW are used as data strobes, while DREQ and DACK serve as handshake signals. Table 49. Control bits for Generic DMA transfers Description GDMA read/write (opcode = 00h/01h) DMA Configuration register ATA_MODE DMA_MODE[1:0] DIS_XFER_CNT MODE[1:0] WIDTH set to logic 0 (non-ATA transfer) set to logic 1 (ATA transfer) determines MDMA timing for DIOR and DIOW strobes Table 56 MDMA (master) read/write (opcode = 06h/07h) Reference Control bits disables use of DMA transfer disables use of DMA transfer counter counter determines active read/write determines active data data strobe signals strobe(s) selects DMA bus width: 8 or 16 bits selects DMA bus width: 8 or 16 bits ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 46 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Control bits for Generic DMA transfers ...continued Description GDMA read/write (opcode = 00h/01h) MDMA (master) read/write (opcode = 06h/07h) determines whether data is to be byte swapped or normal; applicable only in 16-bit mode input EOT is not used set to logic 1 (master) selects polarity of DMA handshake signals Table 58 Reference Table 49. Control bits DMA Hardware register ENDIAN[1:0] determines whether data is to be byte swapped or normal; applicable only in 16-bit mode selects polarity of the EOT signal set to logic 0 (slave) selects polarity of DMA handshake signals EOT_POL MASTER ACK_POL, DREQ_POL, WRITE_POL, READ_POL Table 50. Control bits for IDE-specified DMA transfers Description MDMA read/write (opcode = 06h/07h) Reference Control bits DMA Configuration register ATA_MODE DMA_MODE[1:0] PIO_MODE[2:0] MASTER set to logic 1 (ATA transfer) selects MDMA mode; timing are ATA(PI) compatible selects PIO mode; timing are ATA(PI) compatible set to logic 0 Table 58 Table 56 DMA Hardware register Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the other control signals are not 3-stated. 9.4.1 DMA Command register (address: 30h) The DMA Command register is a 1-byte register (for bit allocation, see Table 51) that initiates all DMA transfer activity on the DMA controller. The register is write-only: reading it will return FFh. Remark: The DMA bus will be in 3-state, until a DMA command is executed. Table 51. Bit Symbol Reset Bus reset Access 1 1 W 1 1 W 1 1 W DMA Command register: bit allocation 7 6 5 4 1 1 W 3 1 1 W 2 1 1 W 1 1 1 W 0 1 1 W DMA_CMD[7:0] ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 47 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller DMA Command register: bit description Symbol DMA_CMD[7:0] Description DMA command code, see Table 53. PIO read or write that started using the DMA Command register only performs a 16-bit transfer. Table 52. Bit 7 to 0 Table 53. Code 00h DMA commands Name GDMA Read Description Generic DMA IN token transfer (slave mode only): Data is transferred from the external DMA bus to the internal buffer. Strobe: DIOW by the external DMA controller. Generic DMA OUT token transfer (slave mode only): Data is transferred from the internal buffer to the external DMA bus. Strobe: DIOR by the external DMA controller. reserved Multi-word DMA Read: Data is transferred from the external DMA bus to the internal buffer. Multi-word DMA Write: Data is transferred from the internal buffer to the external DMA bus. Read at address 1F0h: Initiates a PIO read cycle from Task File 1F0. Before issuing this command, the task file byte count must be programmed at address 1F4h (LSByte) and 1F5h (MSByte). Poll BSY status bit for ATAPI device: Starts repeated PIO read commands to poll the BSY status bit of the ATAPI device. When BSY = 0, polling is terminated and an interrupt is generated. The interrupt can be masked but the interrupt bit will still be set. Therefore, you can manually poll this interrupt bit. Read Task Files: Reads all task files. When Task File Index is set to logic 0, this command reads all registers, except 1F0h and 1F7h. If Task File Index is not logic 0, the Task register of the address set in the Task File register will be read. When the reading is completed, an interrupt is generated. The interrupt can be masked off, however, the interrupt bit will still be set. Therefore, you can manually poll this interrupt bit. reserved Validate Buffer (for debugging only): Request from the microcontroller to validate the endpoint buffer, following an ATA-to-USB data transfer. Clear Buffer: Request from the microcontroller to clear the endpoint buffer, after a DMA-to-USB data transfer. Logic 1 clears the TX buffer of the indexed endpoint; the RX buffer is not affected. The TX buffer is automatically cleared once data is sent on the USB bus. This bit is set only when it is necessary to forcefully clear the buffer. Remark: If using double buffer, to clear both the buffers issue the Clear Buffer command two times, that is, set and clear this bit two times. 01h GDMA Write 02h to 05h 06h 07h 0Ah MDMA Read MDMA Write Read 1F0 0Bh Poll BSY 0Ch Read Task Files 0Dh 0Eh Validate Buffer 0Fh Clear Buffer 10h Restart Restart: Request from the microcontroller to move the buffer pointers to the beginning of the endpoint FIFO. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 48 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller DMA commands ...continued Name Reset DMA Description Reset DMA: Initializes the DMA core to its power-on reset state. Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK, DIOW and DIOR handshake pins will temporarily be asserted. This can confuse the external DMA controller. To prevent this, start the external DMA controller only after the DMA reset. Table 53. Code 11h 12h 13h MDMA stop GDMA stop MDMA stop: This command immediately stops the MDMA data transfer. This is applicable for commands 06h and 07h only. GDMA stop: This command stops the GDMA data transfer. Any data in the OUT endpoint that is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint will be written to the endpoint buffer. An interrupt bit will be set to indicate the completion of the DMA Stop command. Remark: For the DMA OUT transfer, if the DMA Burst Counter register is programmed to some value, for example 512 bytes, and if a GDMA Stop command is issued in the middle of a transfer, the transfer will continue until the end of the burst size (512 bytes). Issuing a GDMA Stop command does not allow the ISP1583 to stop in the middle of the burst. It can only be stopped in between bursts. 14h to 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h to FFh Read Task File register 1F1h Read Task File register 1F2h Read Task File register 1F3h Read Task File register 1F4h Read Task File register 1F5h Read Task File register 1F6h Read Task File register 3F6h Read Task File register 3F7h - reserved Read Task File register 1F1h: When reading is completed, an interrupt is generated. Read Task File register 1F2h: When reading is completed, an interrupt is generated. Read Task File register 1F3h: When reading is completed, an interrupt is generated. Read Task File register 1F4h: When reading is completed, an interrupt is generated. Read Task File register 1F5h: When reading is completed, an interrupt is generated. Read Task File register 1F6h: When reading is completed, an interrupt is generated. Read Task File register 3F6h: When reading is completed, an interrupt is generated. Read Task File register 3F7h: When reading is completed, an interrupt is generated. reserved 9.4.2 DMA Transfer Counter register (address: 34h) This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in Table 54. For IN endpoint -- Because there is a FIFO in the ISP1583 DMA controller, some data may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and the maximum delay time for data to be shifted to endpoint buffer is 60 ns. For OUT endpoint -- Data will not be cleared from the endpoint buffer, until all the data is read from the DMA FIFO. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 49 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when it reaches zero. Table 54. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W Table 55. Bit 31 to 24 23 to 16 15 to 8 7 to 0 0 0 R/W 0 0 R/W 7 0 0 R/W 6 0 0 R/W 5 0 0 R/W 15 0 0 R/W 14 0 0 R/W 13 0 0 R/W 23 0 0 R/W 22 0 0 R/W 21 DMA Transfer Counter register: bit allocation 31 30 29 28 0 0 R/W 20 0 0 R/W 12 0 0 R/W 4 0 0 R/W 27 0 0 R/W 19 0 0 R/W 11 0 0 R/W 3 0 0 R/W 26 0 0 R/W 18 0 0 R/W 10 0 0 R/W 2 0 0 R/W 25 0 0 R/W 17 0 0 R/W 9 0 0 R/W 1 0 0 R/W 24 0 0 R/W 16 0 0 R/W 8 0 0 R/W 0 0 0 R/W DMACR4 = DMACR[31:24] DMACR3 = DMACR[23:16] DMACR2 = DMACR[15:8] DMACR1 = DMACR[7:0] DMA Transfer Counter register: bit description Symbol DMACR4 = DMACR[31:24] DMACR3 = DMACR[23:16] DMACR2 = DMACR[15:8] DMACR1 = DMACR[7:0] Description DMA transfer counter byte 4 (MSByte) DMA transfer counter byte 3 DMA transfer counter byte 2 DMA transfer counter byte 1 (LSByte) 9.4.3 DMA Configuration register (address: 38h) This register defines the DMA configuration for GDMA mode. The DMA Configuration register consists of 2 bytes. The bit allocation is given in Table 56. Table 56. Bit Symbol Reset Bus reset Access DMA Configuration register: bit allocation 15 reserved 14 13 ATA_ MODE 0 0 R/W 12 11 10 9 PIO_MODE[2:0] 0 0 R/W 0 0 R/W 0 0 R/W 8 DMA_MODE[1:0] 0 0 R/W 0 0 R/W ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 50 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 6 5 reserved 0 0 R/W 4 3 MODE[1:0] 0 0 R/W 2 1 reserved 0 WIDTH 1 1 R/W Bit Symbol Reset Bus reset Access 7 DIS_ XFER_CNT 0 0 R/W Table 57. Bit 15 to 14 13 DMA Configuration register: bit description Symbol ATA_MODE Description[1] reserved ATA Mode: Mode selection of the DMA core. 0 -- Configures the DMA core for non-ATA mode. Used when issuing DMA commands 00h and 01h. 1 -- Configures the DMA core for ATA or MDMA mode. Used when issuing DMA commands 02h to 07h, 0Ah and 0Ch; also used when directly accessing Task File registers. 12 to 11 DMA_MODE [1:0] DMA Mode: These bits affect the timing for MDMA mode. 00 -- MDMA mode 0: ATA(PI) compatible timing 01 -- MDMA mode 1: ATA(PI) compatible timing 10 -- MDMA mode 2: ATA(PI) compatible timing 11 -- MDMA mode 3: enables the DMA Strobe Timing register (see Table 78 and Table 79) for non-standard strobe durations; only used in MDMA mode 10 to 8 PIO_MODE [2:0][2] PIO Mode: These bits affect the PIO timing. 000 to 100 -- PIO mode 0 to 4: ATA(PI) compatible timing 101 to 111 -- reserved Disable Transfer Count: Logic 1 disables the DMA Transfer Counter (see Table 54). The transfer counter can be disabled only in GDMA slave mode; in master mode the counter is always enabled. reserved Mode: These bits only affect GDMA (slave) and MDMA (master) handshake signals. 00 -- DIOR (master) or DIOW (slave): strobes data from the DMA bus into the ISP1583; DIOW (master) or DIOR (slave): puts data from the ISP1583 on the DMA bus. 01 -- DIOR (master) or DACK (slave): strobes data from the DMA bus into the ISP1583; DACK (master) or DIOR (slave): puts data from the ISP1583 on the DMA bus. 10 -- DACK (master and slave): strobes data from the DMA bus into the ISP1583 and also puts data from the ISP1583 on the DMA bus. 11 -- reserved 7 DIS_XFER_ CNT MODE[1:0] 6 to 4 3 to 2 1 0 WIDTH reserved Width: This bit selects the DMA bus width for GDMA (slave) and MDMA (master). 0 -- 8-bit data bus 1 -- 16-bit data bus [1] The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is, after configuring the DMA Configuration register). (c) NXP B.V. 2008. All rights reserved. ISP1583_7 Product data sheet Rev. 07 -- 22 September 2008 51 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller [2] PIO read or write that started using the DMA Command register only performs 16-bit transfer. 9.4.4 DMA Hardware register (address: 3Ch) The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 58. This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR and DIOW) and DMA mode (master or slave). It also controls whether the upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes GDMA (slave) and MDMA (master) only. Table 58. Bit Symbol Reset Bus reset Access DMA Hardware register: bit allocation 7 6 5 EOT_POL 0 0 R/W 4 MASTER 0 0 R/W 3 ACK_POL 0 0 R/W 2 DREQ_ POL 1 1 R/W 1 WRITE_ POL 0 0 R/W 0 READ_ POL 0 0 R/W ENDIAN[1:0] 0 0 R/W 0 0 R/W Table 59. Bit 7 to 6 DMA Hardware register: bit description Description Symbol ENDIAN[1:0] Endian: These bits determine whether the data bus is swapped between the internal RAM and the DMA bus. This only applies for modes GDMA (slave) and MDMA (master). 00 -- Normal data representation; 16-bit bus: MSByte on DATA[15:8] and LSByte on DATA[7:0]. 01 -- Swapped data representation; 16-bit bus: MSByte on DATA[7:0] and LSByte on DATA[15:8]. 10 -- reserved 11 -- reserved Remark: While operating with the 8-bit data bus, bits ENDIAN[1:0] must always be set to logic 00. 5 EOT_POL EOT Polarity: Selects the polarity of the End-Of-Transfer input; used in GDMA slave mode only. 0 -- EOT is active LOW 1 -- EOT is active HIGH 4 MASTER Master or Slave Selection: Selects DMA master or slave mode. 0 -- GDMA slave mode 1 -- MDMA master mode 3 ACK_POL Acknowledgment Polarity: Selects the DMA acknowledgment polarity. 0 -- DACK is active LOW 1 -- DACK is active HIGH ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 52 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller DMA Hardware register: bit description ...continued Description DREQ Polarity: Selects the DMA request polarity. 0 -- DREQ is active LOW 1 -- DREQ is active HIGH Table 59. Bit 2 Symbol DREQ_POL 1 WRITE_POL Write Polarity: Selects the DIOW strobe polarity. 0 -- DIOW is active LOW 1 -- DIOW is active HIGH 0 READ_POL Read Polarity: Selects the DIOR strobe polarity. 0 -- DIOR is active LOW 1 -- DIOR is active HIGH 9.4.5 Task File registers (addresses: 40h to 4Fh) These registers allow direct access to the internal registers of an ATAPI peripheral using PIO mode. The supported Task File registers and their functions are shown in Table 60. The correct peripheral register is automatically addressed using pins CS1_N, CS0_N, DA2, MODE0/DA1 and BUS_CONF/DA0 (see Table 61). Table 60. Task file 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 3F6 3F7 Table 61. Task file 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 3F6 3F7 Task File register functions ATA function data (16-bit) error/feature sector count sector number/LBA[7:0] cylinder low/LBA[15:8] cylinder high/LBA[23:16] drive/head/LBA[27:24] command alternate status/command drive address ATAPI peripheral register addressing CS1_N HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW CS0_N LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH DA2 LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH MODE0/DA1 LOW LOW HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH BUS_CONF/DA0 LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH ATAPI function data (16-bit) error/feature interrupt reason reserved cylinder low cylinder high drive select status/command alternate status/command reserved ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 53 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller In 8-bit bus mode, 16-bit Task File register 1F0 requires two consecutive write/read accesses before the proper PIO write/read is generated on the IDE interface. The first byte is always the lower byte (LSByte). Other Task File registers can directly be accessed. Writing to Task File registers can be done in any order, except for the Task File register 1F7, which must be written last. Table 62. Task File 1F0 register (address: 40h): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = LOW, BUS_CONF/DA0 = LOW. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 0 0 R/W 7 6 5 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W data (ATA or ATAPI) Table 63. Task File 1F1 register (address: 48h): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = LOW, BUS_CONF/DA0 = HIGH. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 0 0 R/W 7 6 5 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W error/feature (ATA or ATAPI) Table 64. Task File 1F2 register (address: 49h): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 7 6 5 0 0 R/W 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W sector count (ATA) or interrupt reason (ATAPI) Table 65. Task File 1F3 register (address: 4Ah): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 7 6 5 0 0 R/W 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W sector number/LBA[7:0] (ATA), reserved (ATAPI) Table 66. Task File 1F4 register (address: 4Bh): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = LOW, BUS_CONF/DA0 = LOW. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 7 6 5 0 0 R/W 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W cylinder low/LBA[15:8] (ATA) or cylinder low (ATAPI) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 54 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 67. Task File 1F5 register (address: 4Ch): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = LOW, BUS_CONF/DA0 = HIGH. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 7 6 5 0 0 R/W 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W cylinder high/LBA[23:16] (ATA) or cylinder high (ATAPI) Table 68. Task File 1F6 register (address: 4Dh): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 7 6 5 0 0 R/W 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W drive/head/LBA[27:24] (ATA) or drive (ATAPI) Table 69. Task File 1F7 register (address: 44h): bit allocation CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH. Bit Symbol Reset Bus reset Access [1] 7 0 0 W 6 0 0 W 5 0 0 W 4 0 0 W 3 status[1]/command 0 0 W 2 (ATAPI) 0 0 W 1 0 0 W 0 0 0 W command (ATA) or Task File register 1F7 is a write-only register; a read will return FFh. Table 70. Task File 3F6 register (address: 4Eh): bit allocation CS1_N = LOW, CS0_N = HIGH, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 7 6 5 0 0 R/W 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W alternate status/command (ATA or ATAPI) Table 71. Task File 3F7 register (address: 4Fh): bit allocation CS1_N = LOW, CS0_N = HIGH, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH. Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 0 0 R/W 7 6 5 4 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 0 0 R/W drive address (ATA) or reserved (ATAPI) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 55 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 9.4.6 DMA Interrupt Reason register (address: 50h) This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA command is executed. An interrupt source is cleared by writing logic 1 to the corresponding bit. On detecting the interrupt, the external microprocessor must read the DMA Interrupt Reason register and mask it with the corresponding bits in the DMA Interrupt Enable register to determine the source of the interrupt. The bit allocation is given in Table 72. Table 72. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access DMA Interrupt Reason register: bit allocation 15 TEST3 0 0 R 7 6 reserved Table 73. Bit 15 14 reserved 5 13 12 GDMA_ STOP 0 0 R/W 4 READ_1F0 0 0 R/W 11 EXT_EOT 0 0 R/W 3 BSY_ DONE 0 0 R/W 10 INT_EOT 0 0 R/W 2 TF_RD_ DONE 0 0 R/W 9 INTRQ_ PENDING 0 0 R/W 1 CMD_ INTRQ_OK 0 0 R/W 8 DMA_ XFER_OK 0 0 R/W 0 reserved - DMA Interrupt Reason register: bit description Symbol TEST3 Description This bit is set when a DMA transfer for a packet (OUT transfer) terminates before the whole packet is transferred. This bit is a status bit, and the corresponding mask bit of this register is always 0. Writing any value other than 0 has no effect. reserved GDMA Stop: When the GDMA_STOP command is issued to DMA Command registers, it means the DMA transfer has successfully terminated. External EOT: Logic 1 indicates that an external EOT is detected. This is applicable only in GDMA slave mode. Internal EOT: Logic 1 indicates that an internal EOT is detected; see Table 74. Interrupt Pending: Logic 1 indicates that a pending interrupt was detected on pin INTRQ. DMA Transfer OK: Logic 1 indicates that the DMA transfer is completed (DMA Transfer Counter has become zero). This bit is only used in GDMA (slave) mode and MDMA (master) mode. reserved Read 1F0: Logic 1 indicates that the 1F0 FIFO contains unread data and the microcontroller can start reading data. Busy Done: Logic 1 indicates that the BSY status bit has become zero and polling has been stopped. 14 to 13 12 GDMA_STOP 11 10 9 8 EXT_EOT INT_EOT INTRQ_ PENDING DMA_XFER_OK 7 to 5 4 3 READ_1F0 BSY_DONE ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 56 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller DMA Interrupt Reason register: bit description ...continued Symbol TF_RD_DONE CMD_INTRQ_OK Description Task File Read Done: Logic 1 indicates that the Read Task Files command has been completed. Command Interrupt OK: Logic 1 indicates that all bytes from the FIFO have been transferred (DMA Transfer Count zero) and an interrupt on pin INTRQ was detected. reserved Internal EOT-functional relation with DMA_XFER_OK bit DMA_XFER_OK 0 1 1 Description During the DMA transfer, there is a premature termination with short packet. DMA transfer is completed with short packet and the DMA transfer counter has reached 0. DMA transfer is completed without any short packet and the DMA transfer counter has reached 0. Table 73. Bit 2 1 0 Table 74. INT_EOT 1 1 0 - 9.4.7 DMA Interrupt Enable register (address: 54h) This 2-byte register controls the interrupt generation of the source bits in the DMA Interrupt Reason register (see Table 72). The bit allocation is given in Table 75. The bit description is given in Table 73. Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is disabled, with values turning to logic 0. Table 75. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access DMA Interrupt Enable register: bit allocation 15 TEST4 0 0 R 7 6 reserved 14 reserved 5 13 12 IE_GDMA_ STOP 0 0 R/W 4 IE_ READ_1F0 0 0 R/W 11 IE_EXT_ EOT 0 0 R/W 3 IE_BSY_ DONE 0 0 R/W 10 IE_INT_ EOT 0 0 R/W 2 IE_TF_ RD_DONE 0 0 R/W 9 IE_INTRQ_ PENDING 0 0 R/W 1 IE_CMD_ INTRQ_OK 0 0 R/W 8 IE_DMA_ XFER_OK 0 0 R/W 0 reserved - 9.4.8 DMA Endpoint register (address: 58h) This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA transfers. The bit allocation is given in Table 76. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 57 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 76. Bit Symbol Reset Bus reset Access DMA Endpoint register: bit allocation 7 6 reserved Table 77. Bit 7 to 4 3 to 1 0 0 0 R/W 5 4 3 2 EPIDX[2:0] 0 0 R/W 0 0 R/W 1 0 DMADIR 0 0 R/W DMA Endpoint register: bit description Symbol EPIDX[2:0] DMADIR Description reserved Endpoint Index: selects the indicated endpoint for DMA access DMA Direction: 0 -- Selects the RX/OUT FIFO for DMA read transfers 1 -- Selects the TX/IN FIFO for DMA write transfers The DMA Endpoint register must not reference the endpoint that is indexed by the Endpoint Index register (2Ch) at any time. Doing so will result in data corruption. Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not reference the same endpoint on the Endpoint Index register. 9.4.9 DMA Strobe Timing register (address: 60h) This 1-byte register controls the strobe timing for MDMA mode, when bits DMA_MODE[1:0] in the DMA Configuration register have been set to 03h. The bit allocation is given in Table 78. Table 78. Bit Symbol Reset Bus reset Access DMA Strobe Timing register: bit allocation 7 6 reserved Table 79. Bit 7 to 5 4 to 0 DMA_STROBE_ CNT[4:0] 1 1 R/W 1 1 R/W 5 4 3 2 DMA_STROBE_CNT[4:0] 1 1 R/W 1 1 R/W 1 1 R/W 1 0 DMA Strobe Timing register: bit description Symbol Description reserved DMA Strobe Count: These bits select the strobe duration for DMA_MODE = 03h (see Table 56). The strobe duration is (N + 1) cycles[1], with N representing the value of DMA_STROBE_CNT (see Figure 17). [1] The cycle duration indicates the internal clock cycle (33.3 ns/cycle). ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 58 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller x x (N + 1) cycles 004aaa125 Fig 17. Programmable strobe timing 9.4.10 DMA Burst Counter register (address: 64h) Table 80 shows the bit allocation of the 2-byte register. Table 80. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W Table 81. Bit 15 to 13 12 to 0 BURSTCOUNTER [12:0] 0 0 R/W 7 DMA Burst Counter register: bit allocation 15 14 reserved 6 5 0 0 R/W 4 0 0 R/W 0 0 R/W 3 0 0 R/W 13 12 11 10 BURSTCOUNTER[12:8] 0 0 R/W 2 0 0 R/W 0 0 R/W 1 1 1 R/W 0 0 R/W 0 0 0 R/W 9 8 BURSTCOUNTER[7:0] DMA Burst Counter register: bit description Symbol Description reserved Burst Counter: This register defines the burst length. The counter must be programmed to be a multiple of two in 16-bit mode. The value of the burst counter must be programmed so that the burst counter is a factor of the buffer size. It is used to determine the assertion and deassertion of DREQ. 9.5 General registers 9.5.1 Interrupt register (address: 18h) The Interrupt register consists of 4 bytes. The bit allocation is given in Table 82. When a bit is set in the Interrupt register, it indicates that the hardware condition for an interrupt has occurred. When the Interrupt register content is nonzero, the INT output will be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the external microprocessor must read the Interrupt register and mask it with the corresponding bits in the Interrupt Enable register to determine the source of the interrupt. Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset. The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in the DMA Interrupt Reason register (see Table 72 and Table 73). ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 59 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register. Table 82. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 23 EP6TX 0 0 R/W 15 EP2TX 0 0 R/W 7 VBUS 0 0 R/W 22 EP6RX 0 0 R/W 14 EP2RX 0 0 R/W 6 DMA 0 0 R/W Table 83. Bit 31 to 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ISP1583_7 Interrupt register: bit allocation 31 30 29 reserved 21 EP5TX 0 0 R/W 13 EP1TX 0 0 R/W 5 HS_STAT 0 0 R/W 20 EP5RX 0 0 R/W 12 EP1RX 0 0 R/W 4 RESUME 0 0 R/W 19 EP4TX 0 0 R/W 11 EP0TX 0 0 R/W 3 SUSP 0 0 R/W 18 EP4RX 0 0 R/W 10 EP0RX 0 0 R/W 2 PSOF 0 0 R/W 28 27 26 25 EP7TX 0 0 R/W 17 EP3TX 0 0 R/W 9 reserved 1 SOF 0 0 R/W 24 EP7RX 0 0 R/W 16 EP3RX 0 0 R/W 8 EP0SETUP 0 0 R/W 0 BRESET 0 1 R/W Interrupt register: bit description Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX Description reserved logic 1 indicates the endpoint 7 TX buffer as interrupt source logic 1 indicates the endpoint 7 RX buffer as interrupt source logic 1 indicates the endpoint 6 TX buffer as interrupt source logic 1 indicates the endpoint 6 RX buffer as interrupt source logic 1 indicates the endpoint 5 TX buffer as interrupt source logic 1 indicates the endpoint 5 RX buffer as interrupt source logic 1 indicates the endpoint 4 TX buffer as interrupt source logic 1 indicates the endpoint 4 RX buffer as interrupt source logic 1 indicates the endpoint 3 TX buffer as interrupt source logic 1 indicates the endpoint 3 RX buffer as interrupt source logic 1 indicates the endpoint 2 TX buffer as interrupt source logic 1 indicates the endpoint 2 RX buffer as interrupt source logic 1 indicates the endpoint 1 TX buffer as interrupt source logic 1 indicates the endpoint 1 RX buffer as interrupt source logic 1 indicates the endpoint 0 data TX buffer as interrupt source (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 60 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Interrupt register: bit description ...continued Symbol EP0RX EP0SETUP VBUS DMA HS_STAT Description logic 1 indicates the endpoint 0 data RX buffer as interrupt source reserved logic 1 indicates that a SETUP token was received on endpoint 0 logic 1 indicates a transition from LOW to HIGH on VBUS DMA status: Logic 1 indicates a change in the DMA Interrupt Reason register. High-Speed Status: Logic 1 indicates a change from full-speed to high-speed mode (HS connection). This bit is not set, when the system goes into full-speed suspend. Resume Status: Logic 1 indicates that a status change from suspend to resume (active) was detected. Suspend Status: Logic 1 indicates that a status change from active to suspend was detected on the bus. Pseudo SOF Interrupt: Logic 1 indicates that a pseudo SOF or SOF was received. Pseudo SOF is an internally generated clock signal (full-speed: 1 ms period, high-speed: 125 s period) that is not synchronized to the USB bus SOF or SOF. SOF Interrupt: Logic 1 indicates that a SOF or SOF was received. Bus Reset: Logic 1 indicates that a USB bus reset was detected. When bit OTG in the OTG register is set, BRESET will not be set, instead, this interrupt bit will report SE0 on DP and DM for 2 ms. Table 83. Bit 10 9 8 7 6 5 4 3 2 RESUME SUSP PSOF 1 0 SOF BRESET 9.5.2 Chip ID register (address: 70h) This read-only register contains the chip identification and hardware version numbers. The firmware must check this information to determine functions and features supported. The register contains 3 bytes, and the bit allocation is shown in Table 84. Table 84. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R 0 0 R 1 1 R 1 1 R 7 0 0 R 6 0 0 R 5 0 0 R 4 1 1 R 0 0 R 15 0 0 R 14 0 0 R 13 Chip ID register: bit allocation 23 22 21 20 1 1 R 12 CHIPID[7:0] 0 0 R 3 0 0 R 0 0 R 2 0 0 R 1 1 R 1 0 0 R 0 0 R 0 0 0 R 19 0 0 R 11 18 1 1 R 10 17 0 0 R 9 16 1 1 R 8 CHIPID[15:8] VERSION[7:0] ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 61 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Chip ID register: bit description Symbol CHIPID[15:8] CHIPID[7:0] VERSION[7:0] Description Chip ID: lower byte (15h) Chip ID: upper byte (82h) Version: version number (30h) Table 85. Bit 23 to 16 15 to 8 7 to 0 9.5.3 Frame Number register (address: 74h) This read-only register contains the frame number of the last successfully received Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in Table 86. In case of 8-bit access, the register content is returned lower byte first. Table 86. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R Table 87. Bit 15 to 14 13 to 11 10 to 0 0 0 R 0 0 R 0 0 R 7 Frame Number register: bit allocation 15 reserved 6 0 0 R 5 14 13 12 MICROSOF[2:0] 0 0 R 4 SOFR[7:0] 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 3 0 0 R 2 11 10 9 SOFR[10:8] 0 0 R 1 0 0 R 0 8 Frame Number register: bit description Symbol MICROSOF[2:0] SOFR[10:0] Description reserved microframe number frame number 9.5.4 Scratch register (address: 78h) This 16-bit register can be used by the firmware to save and restore information. For example, the device status before it enters the suspend state. The bit allocation is given in Table 88. Table 88. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access ISP1583_7 Scratch register: bit allocation 15 0 0 R/W 7 0 0 R/W 14 0 0 R/W 6 0 0 R/W 13 0 0 R/W 5 0 0 R/W 12 SFIRH[7:0] 0 0 R/W 4 SFIRL[7:0] 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 3 0 0 R/W 2 0 0 R/W 1 0 0 R/W 0 11 10 9 8 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 62 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Scratch register: bit description Symbol SFIRH[7:0] SFIRL[7:0] Description Scratch firmware information register (higher byte) Scratch firmware information register (lower byte) Table 89. Bit 15 to 8 7 to 0 9.5.5 Unlock Device register (address: 7Ch) To protect registers from getting corrupted when the ISP1583 goes into suspend, the write operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when the chip resumes, the Unlock Device command must first be issued to this register before attempting to write to the rest of the registers. This is done by writing unlock code (AA37h) to this register. The bit allocation of the Unlock Device register is given in Table 90. Table 90. Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access W W Table 91. Bit 15 to 0 W W 7 W 6 W 5 Unlock Device register: bit allocation 15 14 13 12 11 10 9 8 ULCODE[15:8] = AAh not applicable not applicable W 4 W 3 W 2 W 1 W 0 ULCODE[7:0] = 37h not applicable not applicable W W W W W Unlock Device register: bit description Symbol ULCODE[15:0] Description Unlock Code: Writing data AA37h unlocks internal registers and FIFOs for writing, following a resume. When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you do not need to issue the Unlock command because the microprocessor is powered and therefore, the RW_N/RD_N, DS_N/WR_N and CS_N signals maintain their states. When bit PWRON is logic 0, the RW_N/RD_N, DS_N/WR_N and CS_N signals are floating because the microprocessor is not powered. To protect the ISP1583 registers from being corrupted during suspend, register write is locked when the chip goes into suspend. Therefore, you need to issue the Unlock command to unlock the ISP1583 registers. 9.5.6 Test Mode register (address: 84h) This 1-byte register allows the firmware to set the DP and DM pins to predetermined states for testing purposes. The bit allocation is given in Table 92. Remark: Only one bit can be set at a time. Either bit FORCEHS or FORCEFS must be set to logic 1 at a time. Of the four bits PRBS, KSTATE, JSTATE and SE0_NAK only one bit must be set at a time. This must be implemented for the Hi-Speed USB logo compliance testing. To exit test mode, power cycle is required. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 63 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 92. Bit Symbol Reset Bus reset Access Test Mode register: bit allocation 7 FORCEHS 0 unchanged R/W Table 93. Bit 7 6 to 5 4 3 2 1 0 6 reserved 5 4 FORCEFS 0 unchanged R/W 3 PRBS 0 0 R/W 2 KSTATE 0 0 R/W 1 JSTATE 0 0 R/W 0 SE0_NAK 0 0 R/W Test Mode register: bit description Description Force High-Speed: Logic 1 forces the hardware to high-speed mode only and disables the chirp detection logic. reserved Force Full-Speed: Logic 1 forces the physical layer to full-speed mode only and disables the chirp detection logic. Predetermined Random Pattern: Logic 1 sets the DP and DM pins to toggle in a predetermined random pattern. K-State: Logic 1 sets the DP and DM pins to the K state. J-State: Logic 1 sets the DP and DM pins to the J state. SE0 NAK: Logic 1 sets the DP and DM pins to a high-speed quiescent state. The device only responds to a valid high-speed IN token with a NAK. Symbol FORCEHS FORCEFS PRBS KSTATE JSTATE SE0_NAK ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 64 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 10. Limiting values Table 94. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(3V3) VCC(I/O) VI Ilu Vesd Parameter supply voltage (3.3 V) input/output supply voltage input voltage latch-up current electrostatic discharge voltage VI < 0 V or VI > VCC(3V3) ILI < 1 A pins DP, DM, VBUS, AGND and DGND other pins Tstg [1] [1] Conditions Min -0.5 -0.5 -0.5 -4000 -2000 -40 Max +4.6 +4.6 VCC(3V3) + 0.5 100 +4000 +2000 +125 Unit V V V mA V V C storage temperature The maximum value for 5 V tolerant pins is 6 V. 11. Recommended operating conditions Table 95. Symbol VCC(3V3) VCC(I/O) VI VIA(I/O) V(pu)OD Tamb Tj Recommended operating conditions Parameter supply voltage (3.3 V) input/output supply voltage input voltage input voltage on analog I/O pins open-drain pull-up voltage ambient temperature junction temperature VCC(3V3) = 3.3 V on pins DP and DM Conditions Min 3.0 1.65 0 0 0 -40 -40 Typ Max 3.6 3.6 VCC(I/O) 3.6 VCC(3V3) +85 +125 Unit V V V V V C C 12. Static characteristics Table 96. Static characteristics: supply pins VCC(3V3) = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; typical values at Tamb = +25 C; unless otherwise specified. Symbol VCC(3V3) Parameter supply voltage (3.3 V) full-speed ICC(3V3)(susp) suspend mode supply current (3.3 V) I/O pad supply voltage VCC(I/O) input/output supply voltage 1.65 3.3 3.6 V Conditions Min 3.0 Typ 3.3 47 19 160 Max 3.6 60 25 Unit V mA mA A Supply voltage ICC(3V3)(oper) operating supply current (3.3 V) high-speed ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 65 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 96. Static characteristics: supply pins ...continued VCC(3V3) = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; typical values at Tamb = +25 C; unless otherwise specified. Symbol ICC(I/O) VCC(1V8) [1] Parameter supply current on pin VCC(I/O) supply voltage (1.8 V) Conditions [1] Min 1.65 Typ 3 1.8 Max 1.95 Unit mA V Regulated supply voltage with voltage converter ICC(I/O) test condition: device set up under the test mode vector and I/O is subjected to external conditions. Table 97. Static characteristics: digital pins VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Input levels VIL VIH VOL VOH ILI [1] Parameter LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage input leakage current Conditions Min - Typ - Max 0.3VCC(I/O) - Unit V V 0.7VCC(I/O) IOL = rated drive IOH = rated drive [1] Output levels 0.15VCC(I/O) V +5 V A 0.8VCC(I/O) -5 - Leakage current This value is applicable to transistor input only. The value will be different if internal pull-up or pull-down resistors are used. Table 98. Static characteristics: OTG detection VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol RDN(VBUS) RUP(DP) Parameter pull-down resistance on pin VBUS pull-up resistance on pin DP Conditions only when bit DISCV is set in the OTG register only when bit DP is set in the OTG register Min 680 300 Typ 800 550 Max 1030 780 Unit Charging and discharging resistor Comparator levels VBVALID VSESEND VBUS valid detection VBUS B-session end detection 2.0 0.2 4.0 0.8 V V Table 99. Static characteristics: analog I/O pins DP and DM VCC(3V3) = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified.[1] Symbol Input levels VDI VCM VSE VIL VIH differential input sensitivity voltage |VI(DP) - VI(DM)| differential common mode voltage includes VDI range range single-ended receiver threshold LOW-level input voltage HIGH-level input voltage 0.2 0.8 0.8 2.0 2.5 2.0 0.8 V V V V V Parameter Conditions Min Typ Max Unit ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 66 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 99. Static characteristics: analog I/O pins DP and DM ...continued VCC(3V3) = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified.[1] Symbol Vth(LH) Vth(HL) Vhys VOL VOH ILZ Capacitance Cin Resistance ZDRV ZINP driver output impedance for driver steady-state drive which is not high-speed capable input impedance exclusive of pull-up/pull-down (for low-/full-speed) 40.5 10 49.5 M input capacitance pin to GND 10 pF Parameter positive-going threshold voltage negative-going threshold voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage OFF-state leakage current RL = 1.5 k to 3.6 V RL = 15 k to GND 0 V < VI < 3.3 V Conditions Min 1.4 0.9 0.4 2.8 -10 Typ Max 1.9 1.5 0.7 0.4 3.6 +10 Unit V V V V V A Schmitt-trigger inputs Output levels Leakage current [1] Pin DP is the USB positive data pin, and pin DM is the USB negative data pin. 13. Dynamic characteristics Table 100. Dynamic characteristics VCC(3V3) = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Reset tW(RESET_N) fXTAL1 RS CL tJ tr tf VI external RESET_N pulse width frequency on pin XTAL1 series resistance load capacitance external clock jitter clock duty cycle rise time fall time input voltage crystal oscillator running 500 45 1.65 12 18 50 1.8 100 500 55 3 3 1.95 s MHz pF ps % ns ns V Crystal oscillator Parameter Conditions Min Typ Max Unit External clock input ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 67 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 101. Dynamic characteristics: analog I/O pins DP and DM VCC(3V3) = 3.3 V 0.3 V; VGND = 0 V; Tamb = -40 C to +85 C; CL = 50 pF; RPU = 1.5 k on DP to VTERM; test circuit of Figure 38; unless otherwise specified. Symbol Parameter Driver characteristics Full-speed mode tFR tFF FRFM VCRS tHSR tHSF rise time fall time differential rise time/fall time matching output signal crossover voltage rise time (10 % to 90 %) fall time (10 % to 90 %) with captive cable with captive cable CL = 50 pF; 10 % to 90 % of |VOH - VOL| CL = 50 pF; 90 % to 10 % of |VOH - VOL| tFR/tFF [1] Conditions Min Typ Max Unit 4 4 90 1.3 500 500 - 20 20 111.11 2.0 - ns ns % V ps ps [1][2] High-speed mode Data source timing Full-speed mode tFEOPT tFDEOP source SE0 interval of EOP source jitter for differential transition to SE0 transition see Figure 18 see Figure 18 [2] [2] 160 -2 - 175 +5 ns ns Receiver timing Full-speed mode tJR1 tJR2 tFEOPR tFST receiver jitter to next transition receiver SE0 interval of EOP width of SE0 interval during differential transition see Figure 19 accepted as EOP; see Figure 18 rejected as EOP; see Figure 20 [2] [2] [2] [2] -18.5 -9 82 - - +18.5 +9 14 ns ns ns ns receiver jitter for paired transitions see Figure 19 [1] [2] Excluding the first transition from the idle state. Characterized only, not tested. Limits guaranteed by design. TPERIOD +3.3 V crossover point differential data lines crossover point extended 0V differential data to SE0/EOP skew N x TPERIOD + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR mgr776 TPERIOD is the bit duration corresponding to the USB data rate. Full-speed timing symbols have a subscript prefix `F', low-speed timing symbols have a prefix `L'. Fig 18. Source differential data-to-EOP transition skew and EOP width ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 68 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller TPERIOD +3.3 V differential data lines 0V t JR consecutive transitions N x TPERIOD + t JR1 paired transitions N x TPERIOD + t JR2 t JR1 t JR2 mgr871 TPERIOD is the bit duration corresponding to the USB data rate. Fig 19. Receiver differential data jitter t FST +3.3 V differential data lines VIH(min) 0V mgr872 Fig 20. Receiver SE0 width tolerance 13.1 Register access timing Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and ALE/A0 refer to the ISP1583 pin. 13.1.1 Generic processor mode BUS_CONF/DA0 = HIGH: generic processor mode 13.1.1.1 8051 mode MODE0/DA1 = HIGH: 8051 mode; see Table 3 Table 102. ISP1583 register access timing parameters: separate address and data buses VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Reading tRLRH tAVRL tRHAX tRLDV tRHDZ tRHSH ISP1583_7 Parameter RW_N/RD_N LOW pulse width address set-up time before RW_N/RD_N LOW address hold time after RW_N/RD_N HIGH RW_N/RD_N LOW to data valid delay RW_N/RD_N HIGH to data outputs 3-state delay RW_N/RD_N HIGH to CS_N HIGH delay Conditions Min > tRLDV 0 0 0 0 Typ - Max 26 15 - Unit ns ns ns ns ns ns (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 69 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 102. ISP1583 register access timing parameters: separate address and data buses ...continued VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tSLRL Writing tWLWH tAVWL tWHAX tDVWH tWHDZ tWHSH tSLWL General Tcy(RW) tRDY1 read or write cycle time READY/IORDY HIGH to RW_N/RD_N or DS_N/WR_N HIGH of the last access 50 91 ns ns DS_N/WR_N LOW pulse width address set-up time before DS_N/WR_N LOW address hold time after DS_N/WR_N HIGH data set-up time before DS_N/WR_N HIGH data hold time after DS_N/WR_N HIGH DS_N/WR_N HIGH to CS_N HIGH delay CS_N LOW to DS_N/WR_N LOW delay 15 0 0 11 5 0 2 ns ns ns ns ns ns ns Parameter CS_N LOW to RW_N/RD_N LOW delay Conditions Min 2 Typ Max Unit ns Tcy(RW) t WHSH t SLWL CS_N t SLRL A[7:0] t RLDV (read) DATA [15:0] t AVRL t RLRH t RHDZ t WHAX t RHAX t RHSH RW_N/RD_N t AVWL (write) DATA [15:0] t DVWH t WLWH DS_N/WR_N 004aaa301 t WHDZ Fig 21. ISP1583 register access timing: separate address and data buses (8051 mode) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 70 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller DS_N/WR_N, RW_N/RD_N READY/IORDY t RDY1 004aaa920 Fig 22. ISP1583 ready signal timing 13.1.1.2 Freescale mode MODE0/DA1 = LOW: Freescale mode; see Table 3 Table 103. ISP1583 register access timing parameters: separate address and data buses VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Reading or writing tWLWH tAVWL tWHAX tDVWH tWHDZ tWHSH tI1VI2L tI2HI1X General Tcy(RW) tRDY1 read or write cycle time READY/IORDY HIGH to DS_N/WR_N HIGH of the last access 50 91 ns ns DS_N/WR_N LOW pulse width address set-up time before DS_N/WR_N LOW address hold time after DS_N/WR_N HIGH data set-up time before DS_N/WR_N HIGH data hold time after DS_N/WR_N HIGH DS_N/WR_N HIGH to CS_N HIGH delay RW_N/RD_N set-up time before DS_N/WR_N LOW RW_N/RD_N hold time after DS_N/WR_N HIGH 15 0 0 11 5 0 0 0 ns ns ns ns ns ns ns ns Conditions Min Typ Max Unit ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 71 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Tcy(RW) t WHSH CS_N t WHAX AD [7:0] (read) DATA [15:0] t AVWL (write) DATA [15:0] t WHDZ t I1VI2L DS_N/WR_N t DVWH t WLWH t I2HI1X read RW_N/RD_N write 004aaa379 Fig 23. ISP1583 register access timing: separate address and data buses (Freescale mode) DS_N/WR_N READY/IORDY t RDY1 004aaa380 Fig 24. ISP1583 ready signal timing ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 72 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller RW_N/RD_N or DS_N/WR_N EOT(1) 36 ns (min) DREQ t h1 004aaa378 (1) Programmable polarity: shown as active LOW. Remark: EOT must be valid for 36 ns (minimum) when pins RW_N/RD_N and DS_N/WR_N are active. Fig 25. EOT timing in generic processor mode 13.1.2 Split bus mode 13.1.2.1 ALE function 8051 mode * BUS_CONF/DA0 = LOW: split bus mode * MODE1 = LOW: ALE function - MODE0/DA1 = HIGH: 8051 mode; see Table 3 Table 104. ISP1583 register access timing parameters: multiplexed address/data bus VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Reading tRLRH tRLDV tRHDZ tRHSH tLLRL Writing tWLWH tDVWH tLLWL tWHDZ tWHSH General Tcy(RW) tAVLL read or write cycle time address set-up time before ALE/A0 LOW 80 0 ns ns DS_N/WR_N LOW pulse width data set-up time before DS_N/WR_N HIGH ALE/A0 LOW to DS_N/WR_N LOW delay data hold time after DS_N/WR_N HIGH DS_N/WR_N HIGH to CS_N HIGH delay 15 5 0 5 0 ns ns ns ns ns RW_N/RD_N LOW pulse width RW_N/RD_N LOW to data valid delay RW_N/RD_N HIGH to data outputs 3-state delay RW_N/RD_N HIGH to CS_N HIGH delay ALE/A0 LOW set-up time before RW_N/RD_N LOW > tRLDV 0 0 0 25 15 ns ns ns ns ns Parameter Conditions Min Typ Max Unit ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 73 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Tcy(RW) CS_N t WHSH t RLDV (read) AD [7:0] address data t RHDZ t LLRL RW_N/RD_N t RLRH t RHSH t WHDZ (write) AD [7:0] address data t LLWL DS_N/WR_N t DVWH t WLWH t AVLL ALE/A0 004aaa382 Fig 26. ISP1583 register access timing: multiplexed address/data bus (8051 mode) Freescale mode * BUS_CONF/DA0 = LOW: split bus mode * MODE1 = LOW: ALE function - MODE0/DA1 = LOW: Freescale mode; see Table 3 Table 105. ISP1583 register access timing parameters: multiplexed address/data bus VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tWLWH tDVWH tWHDZ tWHSH General Tcy(RW) tI1VLL tLLI2L tI2HI1X read or write cycle time RW_N/RD_N set-up time before ALE/A0 LOW ALE/A0 LOW to DS_N/WR_N LOW delay RW_N/RD_N hold time after DS_N/WR_N HIGH 80 5 5 5 ns ns ns ns Parameter DS_N/WR_N LOW pulse width data set-up time before DS_N/WR_N HIGH data hold time after DS_N/WR_N HIGH DS_N/WR_N HIGH to CS_N HIGH delay Conditions Min 15 5 5 0 Typ Max Unit ns ns ns ns Reading or writing ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 74 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Tcy(RW) CS_N t WHSH (read) AD [7:0] address data t WHDZ (write) AD [7:0] address data t I1VLL t LLI2L DS_N/WR_N t DVWH t WLWH RW_N/RD_N t I2HI1X ALE/A0 004aaa381 Fig 27. ISP1583 register access timing: multiplexed address/data bus (Freescale mode) 13.1.2.2 A0 function 8051 mode * BUS_CONF/DA0 = LOW: split bus mode * MODE1 = HIGH: A0 function - MODE0/DA1 = HIGH: 8051 mode; see Table 3 Table 106. ISP1583 register access timing parameters: multiplexed address/data bus VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Reading tRLDV tRHDZ tRHSH tRLRH tWHRH Writing tA0WL tAVWH tDVWH tWHDZ tWHSH tWLWH ISP1583_7 Conditions Min 0 0 > tRLDV 40 0 5 5 5 0 15 Typ - Max 26 15 - Unit ns ns ns ns ns ns ns ns ns ns ns RW_N/RD_N LOW to data valid delay RW_N/RD_N HIGH to data outputs 3-state delay RW_N/RD_N HIGH to CS_N HIGH delay RW_N/RD_N LOW pulse width DS_N/WR_N HIGH to RW_N/RD_N HIGH delay ALE/A0 set-up time before DS_N/WR_N LOW address set-up time before DS_N/WR_N HIGH data set-up time before DS_N/WR_N HIGH data hold time after DS_N/WR_N HIGH DS_N/WR_N HIGH to CS_N HIGH delay DS_N/WR_N LOW pulse width (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 75 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 106. ISP1583 register access timing parameters: multiplexed address/data bus ...continued VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter tWHWH General Tcy(RW) read or write cycle time 50 ns DS_N/WR_N HIGH (address) to DS_N/WR_N HIGH (data) delay Conditions Min 40 Typ Max Unit ns t A0WL ALE/A0 Tcy(RW) t WHSH CS_N t RLDV (read) AD [7:0] address t RLRH RW_N/RD_N data t RHSH t RHDZ t AVWH DS_N/WR_N t WHRH t WHDZ (write) AD [7:0] address data t DVWH t WLWH DS_N/WR_N t WHWH RW_N/RD_N 004aaa383 Fig 28. ISP1583 register access timing: multiplexed address/data bus (A0 function and 8051 mode) Freescale mode * BUS_CONF/DA0 = LOW: split bus mode * MODE1 = HIGH: A0 function - MODE0/DA1 = LOW: Freescale mode; see Table 3 Table 107. ISP1583 register access timing parameters: multiplexed address/data bus VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Reading tRLDV tRHDZ ISP1583_7 Conditions Min 0 Typ - Max 26 15 Unit ns ns DS_N/WR_N LOW to data valid delay DS_N/WR_N HIGH to data outputs 3-state delay (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 76 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 107. ISP1583 register access timing parameters: multiplexed address/data bus ...continued VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter tRHSH tRLRH tWHRH Writing tA0WL tAVWH tDVWH tWHDZ tWHSH tWLWH tWHWH General Tcy(RW) tI2HI1X read or write cycle time RW_N/RD_N hold time after DS_N/WR_N HIGH 50 5 ns ns ALE/A0 set-up time before DS_N/WR_N LOW address set-up time before DS_N/WR_N HIGH data set-up time before DS_N/WR_N HIGH data hold time after DS_N/WR_N HIGH DS_N/WR_N HIGH to CS_N HIGH delay DS_N/WR_N LOW pulse width DS_N/WR_N HIGH (address) to DS_N/WR_N HIGH (data written) delay 0 5 5 5 0 15 40 ns ns ns ns ns ns ns DS_N/WR_N HIGH to CS_N HIGH delay DS_N/WR_N LOW pulse width DS_N/WR_N HIGH (address) to DS_N/WR_N HIGH (data read) delay Conditions Min 0 > tRLDV 40 Typ Max Unit ns ns ns ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 77 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller t A0WL ALE/A0 Tcy(RW) t WHSH CS_N t RLDV (read) AD [7:0] address data t RHDZ t RLRH RW_N/RD_N t RHSH t AVWH DS_N/WR_N t WHRH t WHDZ (write) AD [7:0] address data t DVWH t WLWH DS_N/WR_N t I2HI1X t WHWH RW_N/RD_N 004aaa384 Fig 29. ISP1583 register access timing: multiplexed address/data bus (A0 function and Freescale mode) DIOR, DIOW (1) 36 ns (min) EOT(1) DREQ t h1 004aaa926 (1) Programmable polarity: shown as active LOW. Remark: EOT must be valid for 36 ns (minimum) when DIOR or DIOW is active. Fig 30. EOT timing in split bus mode ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 78 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 13.2 DMA timing 13.2.1 PIO mode Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and ALE/A0 refer to the ISP1583 pin. Table 108. PIO mode timing parameters VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy1(min) read or write cycle time tsu1(min) tw1(min) tw2(min) tsu2(min) th2(min) tsu3(min) th3(min) td2(max) th1(min) tsu4(min) tsu5(min) tw3(max) [1] Conditions [1] Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Unit 600 70 [1] [1] 383 50 125 45 20 35 5 30 15 35 0 1250 240 30 100 30 15 20 5 30 10 35 0 1250 180 30 80 70 30 10 20 5 30 10 35 0 1250 120 25 70 25 20 10 20 5 30 10 35 0 1250 ns ns ns ns ns ns ns ns ns ns ns ns ns address to DIOR or DIOW on set-up time DIOR or DIOW pulse width DIOR/DIOW recovery time data set-up time before DIOW off data hold time after DIOW off data set-up time before DIOR on data hold time after DIOR off data to 3-state delay after DIOR off address hold time after DIOR or DIOW off READY/IORDY after DIOR or DIOW on set-up time read data to READY/IORDY HIGH set-up time READY/IORDY LOW pulse width [3] [2] 165 60 30 50 5 30 20 35 0 1250 [3] Tcy1 is the total cycle time, consisting of command active time tw1 and command recovery (inactive) time tw2, that is, Tcy1 = tw1 + tw2. Minimum timing requirements for Tcy1, tw1 and tw2 must all be met. As Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. td2 specifies the time after DIOR is negated, when the data bus is no longer driven by the device (3-state). If READY/IORDY is LOW at tsu4, the host waits until READY/IORDY is made HIGH before the PIO cycle is completed. In that case, tsu5 must be met for reading (tsu3 does not apply). When READY/IORDY is HIGH at tsu4, tsu3 must be met for reading (tsu5 does not apply). [2] [3] ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 79 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller T cy1 device(1) address valid t su1 t h1 DIOR, DIOW (4) t w1 t w2 (write) DATA [7:0] (2) t su2 t h2 (read) DATA [7:0] (2) t su3 t h3(min) t d2 READY/IORDY (3a) HIGH t su4 READY/IORDY (3b) t su5 READY/IORDY (3c) 004aaa921 t su4 t w3 (1) The device address consists of signals CS1_N, CS0_N, DA2, DA1 and DA0. (2) The data bus width depends on the PIO access command used. The Task File register access uses 8 bits (DATA[7:0]), except for Task File register 1F0 that uses 16 bits (DATA[15:0]). DMA commands 04h and 05h also use a 16-bit data bus. (3) The device can negate READY/IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the current cycle after tsu4, following the assertion of DIOR or DIOW. The following three cases are distinguished: a) Device keeps READY/IORDY released (high-impedance): no wait state is generated. b) Device negates READY/IORDY during tsu4, but re-asserts READY/IORDY before tsu4 expires: no wait state is generated. c) Device negates READY/IORDY during tsu4 and keeps READY/IORDY negated for at least 5 ns after tsu4 expires: a wait state is generated. The cycle is completed as soon as READY/IORDY is re-asserted. For extended read cycles (DIOR asserted), the read data on lines DATAn must be valid at td1 before READY/IORDY is asserted. (4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals. Fig 31. PIO mode timing ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 80 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 13.2.2 GDMA slave mode * Bits MODE[1:0] = 00: data strobes DIOR (read) and DIOW (write); see Figure 32 * Bits MODE[1:0] = 01: data strobes DIOR (read) and DACK (write); see Figure 33 * Bits MODE[1:0] = 10: data strobes DACK (read and write); see Figure 34 Table 109. GDMA slave mode timing parameters VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy1 tsu1 td1 th1 tw1 tw2 td2 th2 th3 tsu2 tsu3 ta1 read or write cycle time DREQ set-up time before first DACK on DREQ on delay after last strobe off DREQ hold time after last strobe on DIOR or DIOW pulse width DIOR or DIOW recovery time read data valid delay after strobe on read data hold time after strobe off write data hold time after strobe off write data set-up time before strobe off DACK set-up time before DIOR/DIOW assertion DACK deassertion after DIOR/DIOW deassertion Conditions Min 75 10 33.33 0 39 36 1 10 0 0 Typ Max 53 600 20 5 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns DREQ(2) tsu1 tw1 DACK(1) tsu3 DIOR or DIOW(1) td2 (read) DATA[15:0] tsu2 (write) DATA[15:0] mgt500 Tcy1 th1 td1 tw2 th2 ta1 th3 DREQ is continuously asserted, until the last transfer is done or the FIFO is full. Data strobes: DIOR (read), DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 32. GDMA slave mode timing: DIOR (master) and DIOW (slave) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 81 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller DREQ(2) tsu3 tw1 Tcy1 td1 th1 tsu1 DACK(1) td2 DIOR or DIOW(1) th2 ta1 (read) DATA[15:0] tsu2 th3 (write) DATA[15:0] mgt502 DREQ is asserted for every transfer. Data strobes: DIOR (read), DACK (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 33. GDMA slave mode timing: DIOR (master) or DACK (slave) DREQ(2) tsu1 DACK(1) td2 HIGH th2 (read) DATA[15:0] tsu2 (write) DATA[15:0] mgt501 tw1 Tcy1 th1 tw2 td1 DIOR or DIOW(1) th3 DREQ is continuously asserted, until the last transfer is done or the FIFO is full. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 34. GDMA slave mode timing: DACK (master and slave) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 82 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 13.2.3 MDMA mode Table 110. MDMA mode timing parameters VCC(I/O) = 1.65 V to 3.6 V; VCC(3V3) = 3.3 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Tcy1(min) tw1(min) td1(max) th3(min) tsu2(min) th2(min) tsu1(min) th1(min) tw2(min) td2(max) td3(max) [1] Parameter read/write cycle time DIOR or DIOW pulse width data valid delay after DIOR on data hold time after DIOR off data set-up time before DIOR or DIOW off data hold time after DIOW off DACK set-up time before DIOR or DIOW on DACK hold time after DIOR or DIOW off DIOR recovery time DIOW recovery time DIOR on to DREQ off delay DIOW on to DREQ off delay DACK off to data lines 3-state delay Conditions [1] [1] Mode 0 480 215 150 5 100 20 0 20 [1] [1] Mode 1 150 80 60 5 30 15 0 5 50 50 40 40 25 Mode 2 120 70 50 5 20 10 0 5 25 25 35 35 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 50 215 120 40 20 Tcy1 is the total cycle time, consisting of command active time tw1 and command recovery (inactive) time tw2, that is, Tcy1 = tw1 + tw2. Minimum timing requirements for Tcy1, tw1 and tw2 must all be met. As Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. DREQ(2) Tcy1 DACK(1) tsu1 DIOR or DIOW(1) td3 tw1 tw2 td2 th1 td1 (write) DATA[15:0] th3 tsu2 th2 (read) DATA[15:0] tsu2 mgt506 (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 35. MDMA master mode timing ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 83 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 14. Application information address data CPU ISP1583 8 AD[7:0] 16 ALE/A0 DATA[15:0] read strobe write strobe chip select RW_N/RD_N DS_N/WR_N CS_N 004aaa273 Fig 36. Typical interface connections for generic processor mode DATA [15:0] DREQ ISP1583 DMA DACK DIOW DIOR ALE/A0 address latch enable ALE INT RW_N/RD_N DS_N/WR_N AD[7:0] interrupt read strobe RD_N write strobe WR_N 8 address or data INTn_N 8051 MICROCONTROLLER P0.7/AD7 to P0.0/AD0 004aaa274 Fig 37. Typical interface connections for split bus mode (slave mode) 15. Test information The dynamic characteristics of analog I/O ports DP and DM are determined using the circuit shown in Figure 38. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 84 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller test point DUT 15 k CL 50 pF mgt495 In full-speed mode, an internal 1.5 k pull-up resistor is connected to pin DP. Fig 38. Load impedance for the DP and DM pins (full-speed mode) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 85 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 16. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm D D1 terminal 1 index area B A SOT804-1 A E1 E A4 c A1 detail X C e1 e 17 L 16 1/2 e b 32 33 vM C A B wM C y1 C y e Eh 1/2 e e2 1 terminal 1 index area 64 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.05 0.00 A4 0.80 0.65 b 0.30 0.18 c 0.2 D 9.05 8.95 D1 8.95 8.55 Dh 4.85 4.55 49 48 X 5 scale 10 mm E 9.05 8.95 E1 8.95 8.55 Eh 4.85 4.55 e 0.5 e1 7.5 e2 7.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT804-1 REFERENCES IEC --JEDEC MO-220 JEITA --- EUROPEAN PROJECTION ISSUE DATE 03-03-26 Fig 39. Package outline SOT804-1 (HVQFN64) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 86 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm SOT543-1 D B A ball A1 index area A E A1 detail X A2 e1 e 1/2 e C b v M C A B w M C y1 C y K J H G F E D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 1/2 e e e2 X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.25 0.15 A2 0.85 0.75 b 0.35 0.25 D 6.1 5.9 E 6.1 5.9 e 0.5 e1 4.5 e2 4.5 v 0.15 w 0.05 y 0.08 y1 0.1 OUTLINE VERSION SOT543-1 REFERENCES IEC --JEDEC MO-195 JEITA --- EUROPEAN PROJECTION ISSUE DATE 00-11-22 02-04-09 Fig 40. Package outline SOT543-1 (TFBGA64) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 87 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 4 x 4 x 0.8 mm SOT969-1 D B A ball A1 index area E A A2 A1 detail X e1 1/2 e e b v w M M CAB C C y1 C y H G F E D C B A e e2 1/2 e ball A1 index area 12345678 X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.1 A1 0.25 0.15 A2 0.85 0.75 b 0.3 0.2 D 4.1 3.9 E 4.1 3.9 e 0.4 e1 2.8 e2 2.8 v 0.15 w 0.05 y 0.08 y1 0.1 OUTLINE VERSION SOT969-1 REFERENCES IEC --JEDEC --JEITA --- EUROPEAN PROJECTION ISSUE DATE 06-09-22 06-09-27 Fig 41. Package outline SOT969-1 (TFBGA64) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 88 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 89 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 17.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 42) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 111 and 112 Table 111. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 235 220 350 220 220 Table 112. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 42. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 90 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 42. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 18. Abbreviations Table 113. Abbreviations Acronym ACK ACPI ASIC ATA ATAPI CRC DMA EMI ESR FS GDMA HS IDE MDMA MMU MO NAK NRZI NYET ISP1583_7 Description Acknowledgement Advanced Configuration and Power Interface Application-Specific Integrated Circuit Advanced Technology Attachment Advanced Technology Attachment Peripheral Interface Cyclic Redundancy Code Direct Memory Access ElectroMagnetic Interference Equivalent Series Resistance Full-Speed Generic DMA High-Speed Integrated Development Environment Multi-word DMA Memory Management Unit Magneto-Optical Not Acknowledged Non-Return-to-Zero Inverted Not Yet (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 91 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 113. Abbreviations ...continued Acronym OTG PCB PHY PID PIE PIO PLL POR SE0 SIE SRP TTL USB Description On-The-Go Printed-Circuit Board Physical Packet IDentifier Parallel Interface Engine Parallel Input/Output Phase-Locked Loop Power-On Reset Single-Ended Zero Serial Interface Engine Session Request Protocol Transistor-Transistor Logic Universal Serial Bus 19. References [1] [2] [3] [4] [5] Universal Serial Bus Specification Rev. 2.0 On-The-Go Supplement to the USB Specification Rev. 1.3 Using ISP1582/3 in a composite device application with alternate settings (AN10071) AT Attachment with Packet Interface Extension (ATA/ATAPI-4), ANSI INCITS 317-1998 (R2003) ISP1582/83 and ISP1761 clearing an IN buffer (AN10045) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 92 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 20. Revision history Table 114. Revision history Document ID ISP1583_7 Modifications: Release date 20080922 Data sheet status Product data sheet Change notice Supersedes ISP1583_6 * * * * * * * * * * * * * Added ISP1583ET2. Added Section 5 "Marking". Added Table 4 "Endpoint access and programmability". Figure 16 "Bus-powered mode": updated the voltage range for VCC(I/O). Removed Section 7.9 "Clear buffer". Table 24 "Mode register: bit allocation": updated the bus reset value for bits CLKAON and PWRON. Table 34 "Endpoint Index register: bit allocation": updated the reset and bus reset values for bit EP0SETUP. Table 38 "Control Function register: bit description": updated description for bit CLBUF. Section 9.3.6 "Endpoint MaxPacketSize register (address: 04h)": updated the first paragraph. Table 48 "Endpoint Type register: bit description": added a remark to the DBLBUF bit description. Figure 32 "GDMA slave mode timing: DIOR (master) and DIOW (slave)": updated. Table 53 "DMA commands": added a remark to GDMA stop. Section 19 "References": updated Ref. 3. Product data sheet Product data sheet Product data Product data Product data Preliminary data 200412038 ISP1583_5 ISP1583-04 ISP1583-03 ISP1583-02 ISP1583-01 - ISP1583_6 ISP1583_5 20070820 20070209 ISP1583-04 20050104 (9397 750 14335) ISP1583-03 20040712 (9397 750 13461) ISP1583-02 20040503 (9397 750 12978) ISP1583-01 20040225 (9397 750 11497) ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 93 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 21. Legal information 21.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 21.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 21.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. SoftConnect -- is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 94 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 23. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Endpoint access and programmability . . . . . . .13 Bus configuration modes . . . . . . . . . . . . . . . . .17 ISP1583 pin status . . . . . . . . . . . . . . . . . . . . . .17 ISP1583 output pin status . . . . . . . . . . . . . . . .17 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .23 Operation truth table for SoftConnect . . . . . . .25 Operation truth table for clock off during suspend . . . . . . . . . . . . . . . . . . . . . . . .25 Operation truth table for back voltage compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Operation truth table for OTG . . . . . . . . . . . . .25 Operation truth table for SoftConnect . . . . . . .26 Operation truth table for clock off during suspend . . . . . . . . . . . . . . . . . . . . . . . .26 Operation truth table for back voltage compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Operation truth table for OTG . . . . . . . . . . . . .27 Operation truth table for SoftConnect . . . . . . .27 Operation truth table for clock off during suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Operation truth table for back voltage compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Operation truth table for OTG . . . . . . . . . . . . .28 Register overview . . . . . . . . . . . . . . . . . . . . . .29 Address register: bit allocation . . . . . . . . . . . .31 Address register: bit description . . . . . . . . . . .31 Mode register: bit allocation . . . . . . . . . . . . . . .32 Mode register: bit description . . . . . . . . . . . . .32 Status of the chip . . . . . . . . . . . . . . . . . . . . . . .33 Interrupt Configuration register: bit allocation .34 Interrupt Configuration register: bit description 34 Debug mode settings . . . . . . . . . . . . . . . . . . . .34 OTG register: bit allocation . . . . . . . . . . . . . . .34 OTG register: bit description . . . . . . . . . . . . . .35 Interrupt Enable register: bit allocation . . . . . .37 Interrupt Enable register: bit description . . . . .37 Endpoint Index register: bit allocation . . . . . . .38 Endpoint Index register: bit description . . . . . .39 Addressing of endpoint buffers . . . . . . . . . . . .39 Control Function register: bit allocation . . . . . .39 Control Function register: bit description . . . . .40 Data Port register: bit allocation . . . . . . . . . . .41 Data Port register: bit description . . . . . . . . . .41 Buffer Length register: bit allocation . . . . . . . .42 Buffer Length register: bit description . . . . . . .42 Table 43. Buffer Status register: bit allocation . . . . . . . . 43 Table 44. Buffer Status register: bit description . . . . . . . 43 Table 45. Endpoint MaxPacketSize register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 46. Endpoint MaxPacketSize register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 47. Endpoint Type register: bit allocation . . . . . . . 44 Table 48. Endpoint Type register: bit description . . . . . . 45 Table 49. Control bits for Generic DMA transfers . . . . . . 46 Table 50. Control bits for IDE-specified DMA transfers . . 47 Table 51. DMA Command register: bit allocation . . . . . . 47 Table 52. DMA Command register: bit description . . . . . 48 Table 53. DMA commands . . . . . . . . . . . . . . . . . . . . . . . 48 Table 54. DMA Transfer Counter register: bit allocation . 50 Table 55. DMA Transfer Counter register: bit description 50 Table 56. DMA Configuration register: bit allocation . . . . 50 Table 57. DMA Configuration register: bit description . . . 51 Table 58. DMA Hardware register: bit allocation . . . . . . . 52 Table 59. DMA Hardware register: bit description . . . . . 52 Table 60. Task File register functions . . . . . . . . . . . . . . . 53 Table 61. ATAPI peripheral register addressing . . . . . . . 53 Table 62. Task File 1F0 register (address: 40h): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 63. Task File 1F1 register (address: 48h): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 64. Task File 1F2 register (address: 49h): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 65. Task File 1F3 register (address: 4Ah): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 66. Task File 1F4 register (address: 4Bh): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 67. Task File 1F5 register (address: 4Ch): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 68. Task File 1F6 register (address: 4Dh): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 69. Task File 1F7 register (address: 44h): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 70. Task File 3F6 register (address: 4Eh): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 71. Task File 3F7 register (address: 4Fh): bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 72. DMA Interrupt Reason register: bit allocation . 56 Table 73. DMA Interrupt Reason register: bit description 56 Table 74. Internal EOT-functional relation with DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . . 57 Table 75. DMA Interrupt Enable register: bit allocation . . 57 Table 76. DMA Endpoint register: bit allocation . . . . . . . 58 Table 77. DMA Endpoint register: bit description . . . . . . 58 continued >> ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 95 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. DMA Strobe Timing register: bit allocation . . .58 DMA Strobe Timing register: bit description . .58 DMA Burst Counter register: bit allocation . . .59 DMA Burst Counter register: bit description . .59 Interrupt register: bit allocation . . . . . . . . . . . .60 Interrupt register: bit description . . . . . . . . . . .60 Chip ID register: bit allocation . . . . . . . . . . . . .61 Chip ID register: bit description . . . . . . . . . . . .62 Frame Number register: bit allocation . . . . . . .62 Frame Number register: bit description . . . . . .62 Scratch register: bit allocation . . . . . . . . . . . . .62 Scratch register: bit description . . . . . . . . . . . .63 Unlock Device register: bit allocation . . . . . . . .63 Unlock Device register: bit description . . . . . . .63 Test Mode register: bit allocation . . . . . . . . . . .64 Test Mode register: bit description . . . . . . . . . .64 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .65 Recommended operating conditions . . . . . . . .65 Static characteristics: supply pins . . . . . . . . . .65 Static characteristics: digital pins . . . . . . . . . . .66 Static characteristics: OTG detection . . . . . . .66 Static characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 100.Dynamic characteristics . . . . . . . . . . . . . . . . . .67 Table 101.Dynamic characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Table 102.ISP1583 register access timing parameters: separate address and data buses . . . . . . . . . .69 Table 103.ISP1583 register access timing parameters: separate address and data buses . . . . . . . . . .71 Table 104.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .73 Table 105.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .74 Table 106.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .75 Table 107.ISP1583 register access timing parameters: multiplexed address/data bus . . . . . . . . . . . . .76 Table 108.PIO mode timing parameters . . . . . . . . . . . . . .79 Table 109.GDMA slave mode timing parameters . . . . . . .81 Table 110.MDMA mode timing parameters . . . . . . . . . . .83 Table 111.SnPb eutectic process (from J-STD-020C) . . .90 Table 112.Lead-free process (from J-STD-020C) . . . . . .90 Table 113.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .91 Table 114.Revision history . . . . . . . . . . . . . . . . . . . . . . . .93 ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 96 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 24. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration ISP1583BS (top view) . . . . . . . .5 Pin configuration ISP1583ET and ISP1583ET2 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin configuration ISP1583ET1 (top view) . . . . . . .6 Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Behavior of bit GLINTENA . . . . . . . . . . . . . . . . . .20 Resistor and electrolytic or tantalum capacitor needed for VBUS sensing . . . . . . . . . . . . . . . . . . .21 Oscilloscope reading: no resistor and capacitor in the network . . . . . . . . . . . . . . . . . . . .21 Oscilloscope reading: with resistor and capacitor in the network . . . . . . . . . . . . . . . . . . . .21 POR timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Clock with respect to the external POR . . . . . . . .22 ISP1583 with a 3.3 V supply . . . . . . . . . . . . . . . .23 Power-sharing mode . . . . . . . . . . . . . . . . . . . . . .24 Interrupt pin status during power off in power-sharing mode . . . . . . . . . . . . . . . . . . . . . .24 Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .26 Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .27 Programmable strobe timing . . . . . . . . . . . . . . . .59 Source differential data-to-EOP transition skew and EOP width . . . . . . . . . . . . . . . . . . . . . .68 Receiver differential data jitter . . . . . . . . . . . . . . .69 Receiver SE0 width tolerance . . . . . . . . . . . . . . .69 ISP1583 register access timing: separate address and data buses (8051 mode) . . . . . . . . .70 ISP1583 ready signal timing . . . . . . . . . . . . . . . .71 ISP1583 register access timing: separate address and data buses (Freescale mode) . . . . .72 ISP1583 ready signal timing . . . . . . . . . . . . . . . .72 EOT timing in generic processor mode . . . . . . . .73 ISP1583 register access timing: multiplexed address/data bus (8051 mode) . . . . . . . . . . . . . .74 ISP1583 register access timing: multiplexed address/data bus (Freescale mode) . . . . . . . . . .75 ISP1583 register access timing: multiplexed address/data bus (A0 function and 8051 mode) .76 ISP1583 register access timing: multiplexed address/data bus (A0 function and Freescale mode) . . . . . . . . . . . .78 EOT timing in split bus mode . . . . . . . . . . . . . . . .78 PIO mode timing . . . . . . . . . . . . . . . . . . . . . . . . .80 GDMA slave mode timing: DIOR (master) and DIOW (slave) . . . . . . . . . . . .81 GDMA slave mode timing: DIOR (master) or DACK (slave) . . . . . . . . . . . . . .82 GDMA slave mode timing: DACK (master and slave). . . . . . . . . . . . . . . . . . .82 MDMA master mode timing . . . . . . . . . . . . . . . . .83 Typical interface connections for generic processor mode . . . . . . . . . . . . . . . . . . . . . . . . . .84 Typical interface connections for split bus mode (slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Load impedance for the DP and DM pins Fig 39. Fig 40. Fig 41. Fig 42. (full-speed mode) . . . . . . . . . . . . . . . . . . . . . . . . 85 Package outline SOT804-1 (HVQFN64) . . . . . . . 86 Package outline SOT543-1 (TFBGA64) . . . . . . . 87 Package outline SOT969-1 (TFBGA64) . . . . . . . 88 Temperature profiles for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 97 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 25. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.13.1 8.13.2 8.14 8.15 8.16 8.16.1 8.16.2 8.16.3 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.4.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . 12 DMA interface, DMA handler and DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hi-Speed USB transceiver . . . . . . . . . . . . . . . 14 MMU and integrated RAM . . . . . . . . . . . . . . . 14 Microcontroller interface and microcontroller handler . . . . . . . . . . . . . . . . . . 14 OTG SRP module . . . . . . . . . . . . . . . . . . . . . . 14 NXP high-speed transceiver . . . . . . . . . . . . . . 15 NXP Parallel Interface Engine (PIE) . . . . . . . . 15 Peripheral circuit . . . . . . . . . . . . . . . . . . . . . . . 15 HS detection . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 NXP Serial Interface Engine (SIE) . . . . . . . . . 15 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reconfiguring endpoints . . . . . . . . . . . . . . . . . 16 System controller . . . . . . . . . . . . . . . . . . . . . . 16 Modes of operation . . . . . . . . . . . . . . . . . . . . . 16 Pins status . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt output pin . . . . . . . . . . . . . . . . . . . . . 18 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 20 VBUS sensing . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 22 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power-sharing mode. . . . . . . . . . . . . . . . . . . . 24 Self-powered mode. . . . . . . . . . . . . . . . . . . . . 26 Bus-powered mode. . . . . . . . . . . . . . . . . . . . . 27 Register description . . . . . . . . . . . . . . . . . . . . 29 Register access . . . . . . . . . . . . . . . . . . . . . . . 30 Initialization registers . . . . . . . . . . . . . . . . . . . 31 Address register (address: 00h) . . . . . . . . . . . 31 Mode register (address: 0Ch) . . . . . . . . . . . . . 31 Interrupt Configuration register (address: 10h). . . . . . . . . . . . . . . . . . . . . . . . . 33 OTG register (address: 12h) . . . . . . . . . . . . . . 34 Session Request Protocol (SRP) . . . . . . . . . . 36 9.2.5 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 Interrupt Enable register (address: 14h) . . . . Data flow registers . . . . . . . . . . . . . . . . . . . . . Endpoint Index register (address: 2Ch) . . . . . Control Function register (address: 28h) . . . . Data Port register (address: 20h) . . . . . . . . . . Buffer Length register (address: 1Ch) . . . . . . Buffer Status register (address: 1Eh) . . . . . . . Endpoint MaxPacketSize register (address: 04h) . . . . . . . . . . . . . . . . . . . . . . . . 9.3.7 Endpoint Type register (address: 08h) . . . . . . 9.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 DMA Command register (address: 30h) . . . . 9.4.2 DMA Transfer Counter register (address: 34h) 9.4.3 DMA Configuration register (address: 38h) . . 9.4.4 DMA Hardware register (address: 3Ch) . . . . . 9.4.5 Task File registers (addresses: 40h to 4Fh) . . 9.4.6 DMA Interrupt Reason register (address: 50h) 9.4.7 DMA Interrupt Enable register (address: 54h) 9.4.8 DMA Endpoint register (address: 58h). . . . . . 9.4.9 DMA Strobe Timing register (address: 60h). . 9.4.10 DMA Burst Counter register (address: 64h). . 9.5 General registers . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Interrupt register (address: 18h). . . . . . . . . . . 9.5.2 Chip ID register (address: 70h) . . . . . . . . . . . 9.5.3 Frame Number register (address: 74h) . . . . . 9.5.4 Scratch register (address: 78h) . . . . . . . . . . . 9.5.5 Unlock Device register (address: 7Ch). . . . . . 9.5.6 Test Mode register (address: 84h) . . . . . . . . . 10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 11 Recommended operating conditions . . . . . . 12 Static characteristics . . . . . . . . . . . . . . . . . . . 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 13.1 Register access timing . . . . . . . . . . . . . . . . . . 13.1.1 Generic processor mode . . . . . . . . . . . . . . . . 13.1.1.1 8051 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.1.2 Freescale mode . . . . . . . . . . . . . . . . . . . . . . . 13.1.2 Split bus mode . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2.1 ALE function. . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2.2 A0 function . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 PIO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 GDMA slave mode . . . . . . . . . . . . . . . . . . . . . 13.2.3 MDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . 15 Test information. . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36 38 38 39 40 41 42 43 44 45 47 49 50 52 53 56 57 57 58 59 59 59 61 62 62 63 63 65 65 65 67 69 69 69 71 73 73 75 79 79 81 83 84 84 86 continued >> ISP1583_7 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 -- 22 September 2008 98 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 89 89 89 89 90 91 92 93 94 94 94 94 94 94 95 97 98 17 17.1 17.2 17.3 17.4 18 19 20 21 21.1 21.2 21.3 21.4 22 23 24 25 Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering . . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 September 2008 Document identifier: ISP1583_7 |
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